wm8953 Wolfson Microelectronics plc, wm8953 Datasheet - Page 28

• Manufacturer Part Number: wm8953
• Description: Low Power Stereo Adc With Pll And Tdm Interface Low Power Stereo Adc With Pll And Tdm Interface
• Manufacturer: Wolfson Microelectronics plc

WM8953
w
INPUT PGA ENABLE
The Input PGAs are enabled using register bits LIN12_ENA, LIN34_ENA, RIN12_ENA and
RIN34_ENA as described in Table 2.
Table 2 Input PGA Enable
REFERENCE VOLTAGES
The analogue circuits in the WM8953 are referenced to VMID (AVDD/2). This voltage is generated
from AVDD via a programmable resistor chain as shown in the audio signal paths diagram on page
15. Together with the external decoupling capacitor on VMID, the programmable resistor chain
results in a slow, normal or fast charging characteristic on VMID. The VMID reference is controlled by
VMID_MODE[1:0].
The analogue circuits in the WM8953 require a bias current. The bias current is enabled by setting
VREF_ENA. Note that the bias current source requires VMID to be enabled also.
Table 3 Reference Voltages
R2 (02h)
R1 (01h)
REGISTER
ADDRESS
REGISTER
ADDRESS
2:1
0
BIT
7
6
5
4
BIT
VMID_MODE
[1:0]
(rw)
VREF_ENA
(rw)
LIN34_ENA
(rw)
LIN12_ENA
(rw)
RIN34_ENA
(rw)
RIN12_ENA
(rw)
LABEL
LABEL
DEFAULT
0b
0b
0b
0b
00b
0b
DEFAULT
LIN34 Input PGA Enable
0 = disabled
1 = enabled
LIN12 Input PGA Enable
0 = disabled
1 = enabled
RIN34 Input PGA Enable
0 = disabled
1 = enabled
RIN12 Input PGA Enable
0 = disabled
1 = enabled
VMID Divider Enable and Select
00 = VMID disabled (for OFF mode)
01 = 2 x 50kΩ divider (Normal mode)
10 = 2 x 250kΩ divider (Standby mode)
11 = 2 x 5kΩ divider (for fast start-up)
VREF Enable (Bias for all analogue
functions)
0 = VREF bias disabled
1 = VREF bias enabled
DESCRIPTION
DESCRIPTION
PD, January 2009, Rev 4.0
Production Data
28