wm8953 Wolfson Microelectronics plc, wm8953 Datasheet - Page 67

• Manufacturer Part Number: wm8953
• Description: Low Power Stereo Adc With Pll And Tdm Interface Low Power Stereo Adc With Pll And Tdm Interface
• Manufacturer: Wolfson Microelectronics plc

w
Production Data
CLOCKING AND SAMPLE RATES
Figure 50 Clocking Scheme
MCLK
MCLK
MCLK is the master clock source
SYSCLK
All internal clocks are derived from SYSCLK.
SYSCLK can be derived directly from MCLK or from the PLL output.
It has a programmable divide by 2 option (MCLKDIV).
ADC_CLKDIV
ADC sample rate is set by ADC_CLKDIV (Master or slave mode).
ADCLRC_RATE
ADCLRC in master mode is derived from BCLK and is controlled by ADCLRC_RATE.
BCLK_DIV
BCLK rate is set by BCLK_DIV in master mode.
The BCLK rate should be high enough to support the selected ADC sample rate.
OPCLKDIV
GPIO Clock output frequency is set by OPCLKDIV.
TOCLK_RATE
A slow clock is used for button/accessory detect de-bounce and for volume update
timeouts (when zero-cross detect is enabled). The frequency of this slow clock is set by
TOCLK_RATE.
MCLK_INV
f/2
PRESCALE
The internal clocks for the ADCs, DSP core functions and digital audio interface are derived from a
common internal clock source, SYSCLK.
SYSCLK can either be derived directly from MCLK, or may be generated from a PLL using MCLK as
an external reference. Many commonly-used audio sample rates can be derived directly from typical
MCLK frequencies; the PLL provides additional flexibility for a wide range of MCLK frequencies. All
clock configurations must be set up before enabling playback to avoid glitches.
The ADC sample rate is selectable, relative to SYSCLK, using ADC_CLKDIV. This must be set
according to the required sampling frequency and depending on the selected clocking mode
(AIF_LRCLKRATE).
In master mode, BCLK is also derived from SYSCLK via a programmable division set by BCLK_DIV.
The BCLK frequency must be set appropriately to support the sample rate of the ADC. The ADCLRC
signal does not automatically match the ADC sample rate; this must be configured using
ADCLRC_RATE as described under “Digital Audio Interface Control”.
A clock (OPCLK) derived from SYSCLK can be output on the GPIO pins to provide clocking for other
parts of the system. This clock is enabled by OPCLK_ENA and its frequency is set by OPCLKDIV.
A slow clock (TOCLK) derived from SYSCLK can be used to de-bounce the button/accessory detect
inputs, and to set the timeout period for volume updates when zero-cross detect is used. This clock
is enabled by TOCLK_ENA and its frequency is set by TOCLK_RATE.
Table 38 to Table 43 show the clocking and sample rate controls for MCLK input, BCLK output (in
master mode), ADCs, and GPIO clock output.
The overall clocking scheme for the WM8953 is illustrated in Figure 50.
f
1
R=f
PLL
2
/f
1
f
2
f/4
f
PLLOUT
SYSCLK_SRC
MCLKDIV[1:0]
00 = MCLK
01 = Reserved
10 = MCLK / 2
11 = Reserved
MCLKDIV[1:0]
BCLK_DIV[3:0]
0000 = SYSCLK
0001 = SYSCLK / 1.5
0010 = SYSCLK / 2
0011 = SYSCLK / 3
0100 = SYSCLK / 4
0101 = SYSCLK / 5.5
0110 = SYSCLK / 6
0111 = SYSCLK / 8
1000 = SYSCLK / 11
1001 = SYSCLK / 12
1010 = SYSCLK / 16
1011 = SYSCLK / 22
1100 = SYSCLK / 24
1101 = SYSCLK / 32
1110 = SYSCLK / 44
1111 = SYSCLK / 48
f/N
OPCLKDIV[3:0]
0000 = SYSCLK
0001 = SYSCLK / 2
0010 = SYSCLK / 3
0011 = SYSCLK / 4
0100 = SYSCLK / 5.5
0101 = SYSCLK / 6
0110 = SYSCLK / 8
0111 = SYSCLK / 12
1000 = SYSCLK /16
1001 – 1111 = Reserved
ADC_CLKDIV[2:0]
000 = SYSCLK
001 = SYSCLK / 1.5
010 = SYSCLK / 2
011 = SYSCLK / 3
100 = SYSCLK / 4
101 = SYSCLK / 5.5
110 = SYSCLK / 6
111 = Reserved
SYSCLK
TOCLK_ENA
f/N
BCLKDIV
[3:0]
Timeout and
De-Bounce
Clock
OPCLK_ENA
en
f/N
ADC_CLKDIV
[2:0]
f/N
OPCLKDIV
f/N
ADCLRC_RATE
[10:0]
f/2
f/2
21
19
OUTPUTS
MASTER
TOCLK_RATE
CLOCK
MODE
f/4
PD, January 2009, Rev 4.0
Button/accessory detect de-bounce,
Volume update timeout
256fs
64fs
ADC DSP
GPIO Clock Output
ADC
ADCLRC
BCLK
WM8953
67