wm8953 Wolfson Microelectronics plc, wm8953 Datasheet - Page 79

• Manufacturer Part Number: wm8953
• Description: Low Power Stereo Adc With Pll And Tdm Interface Low Power Stereo Adc With Pll And Tdm Interface
• Manufacturer: Wolfson Microelectronics plc

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Production Data
POWER MANAGEMENT
POWER MANAGEMENT REGISTERS
The WM8953 has two control registers that allow users to select which functions are active. For
minimum power consumption, unused functions should be disabled. To minimise pop or click noise,
it is important to enable or disable functions in the correct order.
Table 51 Power Management
REGISTER
ADDRESS
R1 (1h)
R2 (02h)
4
2:1
0
15
14
11
9
8
7
6
5
4
1
0
BIT
MICBIAS_ENA
(rw)
VMID_MODE
[1:0]
(rw)
VREF_ENA
(rw)
PLL_ENA
(rw)
TSHUT_ENA
(rw)
OPCLK_ENA
(rw)
AINL_ENA
(rw)
AINR_ENA
(rw)
LIN34_ENA
(rw)
LIN12_ENA
(rw)
RIN34_ENA
(rw)
RIN12_ENA
(rw)
ADCL_ENA
(rw)
ADCR_ENA
(rw)
LABEL
DEFAULT
0b
00b
0b
0b
0b
0b
0b
0b
0b
0b
0b
0b
0b
0b
MICBIAS Enable
0 = OFF (high impedance output)
1 = ON
Vmid Divider Enable and Select
00 = Vmid disabled (for OFF mode)
01 = 2 x 50kΩ divider (Normal mode)
10 = 2 x 250kΩ divider (Standby mode)
11 = 2 x 5kΩ divider (for fast start-up)
VREF Enable (Bias for all analogue
functions)
0 = VREF bias disabled
1 = VREF bias enabled
PLL Enable
0 = disabled
1 = enabled
Thermal Sensor Enable
0 = Thermal sensor disabled
1 = Thermal sensor enabled
GPIO Clock Output Enable
0 = disabled
1 = enabled
Left Input Path Enable
0 = disabled
1 = enabled
Left Input Path Enable
0 = disabled
1 = enabled
LIN34 Input PGA Enable
0 = disabled
1 = enabled
LIN12 Input PGA Enable
0 = disabled
1 = enabled
RIN34 Input PGA Enable
0 = disabled
1 = enabled
RIN12 Input PGA Enable
0 = disabled
1 = enabled
Left ADC Enable
0 = disabled
1 = enabled
Right ADC Enable
0 = disabled
1 = enabled
DESCRIPTION
PD, January 2009, Rev 4.0
WM8953
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