wm8953 Wolfson Microelectronics plc, wm8953 Datasheet - Page 86

• Manufacturer Part Number: wm8953
• Description: Low Power Stereo Adc With Pll And Tdm Interface Low Power Stereo Adc With Pll And Tdm Interface
• Manufacturer: Wolfson Microelectronics plc

WM8953
w
R06 (06h)
Clocking (1)
R07 (07h)
Clocking (2)
REGISTER
ADDRESS
15
14
13
12:9
8:5
4:1
0
15
14
13
BIT
TOCLK_RATE
TOCLK_ENA
OPCLKDIV
[3:0]
BCLK_DIV
[3:0]
SYSCLK_SRC
CLK_FORCE
LABEL
0b
0b
0b
0000b
1110b
0100b
0b
0b
0b
0b
DEFAULT
Timeout Clock Rate
(Selects clock to be used for volume update timeout and
GPIO input de-bounce)
0 = SYSCLK / 2
1 = SYSCLK / 2
Timeout Clock Enable
(This clock is required for volume update timeout and GPIO
input de-bounce)
0 = disabled
1 = enabled
Reserved - Do Not Change
GPIO Output Clock Divider
0000 = SYSCLK
0001 = SYSCLK / 2
0010 = SYSCLK / 3
0011 = SYSCLK / 4
0100 = SYSCLK / 5.5
0101 = SYSCLK / 6
0110 = SYSCLK / 8
0111 = SYSCLK / 12
1000 = SYSCLK / 16
1001 to 1111 = Reserved
Reserved - Do Not Change
BCLK Frequency (Master Mode)
0000 = SYSCLK
0001 = SYSCLK / 1.5
0010 = SYSCLK / 2
0011 = SYSCLK / 3
0100 = SYSCLK / 4
0101 = SYSCLK / 5.5
0110 = SYSCLK / 6
0111 = SYSCLK / 8
1000 = SYSCLK / 11
1001 = SYSCLK / 12
1010 = SYSCLK / 16
1011 = SYSCLK / 22
1100 = SYSCLK / 24
1101 = SYSCLK / 32
1110 = SYSCLK / 44
1111 = SYSCL:K / 48
Reserved - Do Not Change
Reserved - Do Not Change
SYSCLK Source Select
0 = MCLK
1 = PLL output
Forces Clock Source Selection
0 = Existing SYSCLK source (MCLK or PLL output) must be
active when changing to a new clock source.
1 = Allows existing MCLK source to be disabled before
changing to a new clock source.
21
19
(Slower Response)
(Faster Response)
DESCRIPTION
PD, January 2009, Rev 4.0
Production Data
86