wm8953 Wolfson Microelectronics plc, wm8953 Datasheet - Page 65

• Manufacturer Part Number: wm8953
• Description: Low Power Stereo Adc With Pll And Tdm Interface Low Power Stereo Adc With Pll And Tdm Interface
• Manufacturer: Wolfson Microelectronics plc

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Production Data
COMPANDING
The WM8953 supports A-law and µ-law companding. This is selected as shown in Table 36.
Table 36 Companding Control
Companding involves using a piecewise linear approximation of the following equations (as set out
by ITU-T G.711 standard) for data compression:
µ-law (where µ=255 for the U.S. and Japan):
F(x) = ln( 1 + µ|x|) / ln( 1 + µ)
A-law (where A=87.6 for Europe):
F(x) = A|x| / ( 1 + lnA)
F(x) = ( 1 + lnA|x|) / (1 + lnA)
The companded data is also inverted as recommended by the G.711 standard (all 8 bits are inverted
for µ-law, all even data bits are inverted for A-law). The data will be transmitted as the first 8 MSBs
of data.
Companding converts 13 bits (µ-law) or 12 bits (A-law) to 8 bits using non-linear quantization. This
provides greater precision for low amplitude signals than for high amplitude signals, resulting in a
greater usable dynamic range than 8 bit linear quantization. The companded signal is an 8-bit word
comprising sign (1 bit), exponent (3 bits) and mantissa (4 bits).
8-bit mode is selected whenever ADC_COMP=1. The use of 8-bit data allows samples to be passed
using as few as 8 BCLK cycles per LRC frame. When using DSP mode B, 8-bit data words may be
transferred consecutively every 8 BCLK cycles.
8-bit mode (without Companding) may be enabled by setting ADC_COMPMODE=1, when
ADC_COMP=0.
Table 37 8-bit Companded Word Composition
SIGN
R5 (05h)
REGISTER
BIT7
ADDRESS
BIT
2
1
EXPONENT
ADC_COMP
ADC_COMPMODE
BIT[6:4]
LABEL
-1 ≤ x ≤ 1
} for x ≤ 1/A
} for 1/A ≤ x ≤ 1
DEFAULT
0b
0b
ADC Companding Enable
0 = disabled
1 = enabled
ADC Companding Type
0 = µ-law
1 = A-law
MANTISSA
BIT[3:0]
DESCRIPTION
PD, January 2009, Rev 4.0
WM8953
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