wm8953 Wolfson Microelectronics plc, wm8953 Datasheet - Page 42

• Manufacturer Part Number: wm8953
• Description: Low Power Stereo Adc With Pll And Tdm Interface Low Power Stereo Adc With Pll And Tdm Interface
• Manufacturer: Wolfson Microelectronics plc

WM8953
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GPIO CONTROL REGISTERS
Register bit AIF_TRIS, when set, tri-states all audio interface and GPIO pins.
Table 20 GPIO and GPI Pin Function Select
The GPIO pins are also controlled by the register fields described in Table 21. Note the order of
precedence described earlier applies.
Pull-up and pull-down resistors may be enabled on any of GPIO3, GPIO4 or GPIO5. If enabled,
these settings take precedence over all other GPIO selections for that pin. Note that, by default, the
pull-down resistors on GPIO3, GPIO4 and GPIO5 are enabled.
When the GPIO pins are used as inputs, de-bounce and interrupt masking may be controlled on all
GPIO pins (including GPI7 and GPI8) using GPIOn_DEB_ENA and GPIOn_IRQ_ENA bits as shown
in Table 22.
For each of GPIO3, GPIO4 and GPIO5, the register field GPIOn_SEL is used to select the pin
functions of the individual GPIO pins as shown in Table 22. Note that this control has the lowest
precedence and is only effective when GPIOn_PU, GPIOn_PD and AIF_TRIS are set to allow GPIO
functionality on that GPIO pin.
Table 21 GPIO and GPI Control
R9 (09h)
R20 (14h)
R21 (15h)
R22 (16h)
REGISTER
ADDRESS
REGISTER
ADDRESS
15
14
13
12
11:8
7
6
5
4
3:0
7
6
5
4
3:0
7
6
4
3
2
0
BIT
BIT
13
GPIO4_DEB_ENA
GPIO4_IRQ_ENA
GPIO4_PU
GPIO4_PD
GPIO4_SEL[3:0]
GPIO3_DEB_ENA
GPIO3_IRQ_ENA
GPIO3_PU
GPIO3_PD
GPIO3_SEL[3:0]
GPIO5_DEB_ENA
GPIO5_IRQ_ENA
GPIO5_PU
GPIO5_PD
GPIO5_SEL[3:0]
GPI8_DEB_ENA
GPI8_IRQ_ENA
GPI8_ENA
GPI7_DEB_ENA
GPI7_IRQ_ENA
GPI7_ENA
AIF_TRIS
LABEL
LABEL
DEFAULT
0b
0b
0b
0b
1b
0000b
0b
0b
0b
1b
0000b
0b
0b
0b
1b
0000b
0b
0b
0b
0b
0b
0b
DEFAULT
Audio Interface and GPIO Tristate
0 = Audio interface and GPIO pins
operate normally
1 = Tristate all audio interface and GPIO
pins
See Table 22 for GPIO4 control bit
description
See Table 22 for GPIO3 control bit
description
See Table 22 for GPIO5 control bit
description
See Table 22 for GPIn control bit
description
See Table 22 for GPIn control bit
description
DESCRIPTION
PD, January 2009, Rev 4.0
DESCRIPTION
Production Data
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