wm8953 Wolfson Microelectronics plc, wm8953 Datasheet - Page 60

• Manufacturer Part Number: wm8953
• Description: Low Power Stereo Adc With Pll And Tdm Interface Low Power Stereo Adc With Pll And Tdm Interface
• Manufacturer: Wolfson Microelectronics plc

WM8953
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In DSP mode, the left channel MSB is available on either the 1
edge of BCLK (selectable by AIF_LRCLK_INV) following a rising edge of ADCLRC. Right channel
data immediately follows left channel data. Depending on word length, BCLK frequency and sample
rate, there may be unused BCLK cycles between the LSB of the right channel data and the next
sample.
In device master mode, the ADCLRC output will resemble the frame pulse shown in Figure 38 and
Figure 39. In device slave mode, Figure 40 and Figure 41, it is possible to use any length of frame
pulse less than 1/fs, providing the falling edge of the frame pulse occurs greater than one BCLK
period before the rising edge of the next frame pulse.
Figure 38 DSP Mode Audio Interface (mode A, AIF_LRCLK_INV=0, Master)
Figure 39 DSP Mode Audio Interface (mode B, AIF_LRCLK_INV=1, Master)
Figure 40 DSP Mode Audio Interface (mode A, AIF_LRCLK_INV=0, Slave)
st
(mode B) or 2
PD, January 2009, Rev 4.0
nd
Production Data
(mode A) rising
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