wm8953 Wolfson Microelectronics plc, wm8953 Datasheet - Page 72

• Manufacturer Part Number: wm8953
• Description: Low Power Stereo Adc With Pll And Tdm Interface Low Power Stereo Adc With Pll And Tdm Interface
• Manufacturer: Wolfson Microelectronics plc

WM8953
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TOCLK CONTROL
A slow clock (TOCLK) is derived from SYSCLK to enable input de-bouncing and volume update
timeout functions. This clock is enabled by register bit TOCLK_ENA, and its frequency is controlled
by TOCLK_RATE, as described in Table 43.
Table 43 TOCLK Control
USB MODE
It is possible to reduce power consumption by disabling the PLL in some applications. One such
application is when SYSCLK is generated from a 12MHz USB clock source. Setting the
AIF_LRCLKRATE bit as described earlier (see “ADC Sample Rates”) allows a sample rate close to
44.1kHz to be generated with no additional PLL power consumption.
In this configuration, SYSCLK must be driven directly from MCLK and by disabling the PLL. This is
achieved by setting SYSCLK_SRC=0, PLL_ENA=0.
Table 44 USB Mode Control
R6 (06h)
R10 (0Ah)
REGISTER
ADDRESS
REGISTER
ADDRESS
15
14
BIT
10
BIT
TOCLK_RATE
TOCLK_ENA
AIF_LRCLKRATE
LABEL
LABEL
DEFAULT
0b
0b
DEFAULT
0b
Timeout Clock Rate
(Selects clock to be used for volume
update timeout and GPIO input de-
bounce)
0 = SYSCLK / 2
1 = SYSCLK / 2
Timeout Clock Enable
(This clock is required for volume update
timeout and GPIO input de-bounce)
0 = disabled
1 = enabled
0 = Normal mode (256 * fs)
1 = USB mode (272 * fs)
LRCLK Rate
DESCRIPTION
PD, January 2009, Rev 4.0
DESCRIPTION
21
19
(Slower Response)
(Faster Response)
Production Data
72