UPD45128163-A75L ELPIDA [Elpida Memory], UPD45128163-A75L Datasheet - Page 10

• Manufacturer Part Number: UPD45128163-A75L
• Description: 128M-bit Synchronous DRAM 4-bank, LVTTL
• Manufacturer: ELPIDA [Elpida Memory]

10
Write command
burst start address given by the column address to begin the burst
write operation. The first write data in burst mode can input with this
command with subsequent data on following clocks.
Read command
met. This command sets the burst start address given by the column
address.
CBR (auto) refresh command
operation. The refresh address is generated internally.
ready for a row activate command.
command), the PD45128xxx cannot accept any other command.
If the mode register is in the burst write mode, this command sets the
Read data is available after /CAS latency requirements have been
This command is a request to begin the CBR (auto) refresh
Before executing CBR (auto) refresh, all banks must be precharged.
After this cycle, all banks will be in the idle (precharged) state and
During t
(/CS, /CAS = Low, /RAS, /WE = High)
(/CS, /RAS, /CAS = Low, /WE, CKE = High)
(/CS, /CAS, /WE = Low, /RAS = High)
RC
period (from refresh command to refresh or activate
Data Sheet E0344N10 (Ver. 1.0)
Fig.4 Column address and write command
Fig.5 Column address and read command
Fig.6 CBR (auto) refresh command
BA0(A13), BA1(A12)
BA0(A13), BA1(A12)
BA0(A13), BA1(A12)
/RAS
/CAS
/RAS
/CAS
/RAS
/CAS
CKE
CKE
CKE
CLK
CLK
CLK
/WE
/WE
/WE
A10
Add
A10
Add
A10
Add
/CS
/CS
/CS
H
H
H
Col.
Col.
PD45128163