UPD45128163-A75L ELPIDA [Elpida Memory], UPD45128163-A75L Datasheet - Page 31

• Manufacturer Part Number: UPD45128163-A75L
• Description: 128M-bit Synchronous DRAM 4-bank, LVTTL
• Manufacturer: ELPIDA [Elpida Memory]

12.2.2 Precharge Termination in WRITE Cycle
invalid data may be written at the same clock as the precharge command. To prevent this from happening, DQM
must be high at the same clock as the precharge command. This will mask the invalid data.
invalid data may be written at the same clock as the precharge command. To prevent this from happening, DQM
must be high at the same clock as the precharge command. This will mask the invalid data.
During a write cycle, the burst write operation is terminated by a precharge command.
When the precharge command is issued, the burst write operation is terminated and precharge starts.
The same bank can be activated again after t
To issue a precharge command, t
When /CAS latency is 2, the write data written prior to the precharge command will be correctly stored. However,
When /CAS latency is 3, the write data written prior to the precharge command will be correctly stored. However,
Command
Command
CLK
DQM
DQ
CLK
DQM
DQ
T0
T0
WRITE
D1
T1
WRITE
RAS
D1
T1
must be satisfied.
D2
T2
D2
Data Sheet E0344N10 (Ver. 1.0)
T2
RP
from the precharge command.
D3
T3
D3
T3
D4
T4
D4
T4
PRE
D5
T5
PRE
D5
T5
Burst length = X, /CAS latency = 2
Burst length = X, /CAS latency = 3
T6
(t
t
RAS
RP
Hi-Z
T6
t
RP
Hi-Z
must be satisfied)
(t
RAS
T7
ACT
must be satisfied)
T7
ACT
T8
PD45128163
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