UPD45128163-A75L ELPIDA [Elpida Memory], UPD45128163-A75L Datasheet - Page 28

• Manufacturer Part Number: UPD45128163-A75L
• Description: 128M-bit Synchronous DRAM 4-bank, LVTTL
• Manufacturer: ELPIDA [Elpida Memory]

11.4 Read to Write Command Interval
bus must be Hi-Z using DQM before WRITE.
28
During a read cycle, READ can be interrupted by WRITE.
The Read and Write command interval is 1 cycle minimum. There is a restriction to avoid data conflict. The Data
READ can be interrupted by WRITE. DQM must be High at least 3 clocks prior to the Write command.
/CAS latency = 2
/CAS latency = 3
Command
Command
CLK
DQM
DQ
DQM
DQ
Command
T0
CLK
DQM
DQ
READ
READ
T1
T0
Hi-Z
READ
T2
T1
1cycle
WRITE
Q1
T3
D1
Data Sheet E0344N10 (Ver. 1.0)
T2
Q2
Q1
T4
D2
T3
Q3
Q2
T5
D3
T4
Hi-Z is
necessary
Hi-Z is
necessary
T6
D4
T5
WRITE
WRITE
D1
D1
T7
T6
D2
D2
T8
Burst length = 4
T7
Burst length = 8
D3
D3
T9
T8
PD45128163