UPD45128163-A75L ELPIDA [Elpida Memory], UPD45128163-A75L Datasheet - Page 6

• Manufacturer Part Number: UPD45128163-A75L
• Description: 128M-bit Synchronous DRAM 4-bank, LVTTL
• Manufacturer: ELPIDA [Elpida Memory]

1.
2.
3.
4.
5.
6.
7.
8.
9.
10. Auto Precharge ............................................................................................................................... 24
11. Read / Write Command Interval ..................................................................................................... 26
12. Burst Termination ........................................................................................................................... 29
6
Input / Output Pin Function ............................................................................................................. 8
Commands ........................................................................................................................................ 9
Simplified State Diagram ................................................................................................................ 12
Truth Table ...................................................................................................................................... 13
4.1 Command Truth Table............................................................................................................................ 13
4.2 DQM Truth Table ..................................................................................................................................... 13
4.3 CKE Truth Table...................................................................................................................................... 13
4.4 Operative Command Table ................................................................................................................... 14
4.5 Command Truth Table for CKE ............................................................................................................. 17
Initialization ..................................................................................................................................... 18
Programming the Mode Register .................................................................................................. 19
Mode Register ................................................................................................................................. 20
7.1 Burst Length and Sequence ................................................................................................................. 21
Address Bits of Bank-Select and Precharge ................................................................................ 22
Precharge ......................................................................................................................................... 23
10.1
10.2
11.1
11.2
11.3
11.4
12.1
12.2
Read with Auto Precharge ................................................................................................................. 24
Write with Auto Precharge ................................................................................................................. 25
Read to Read Command Interval ....................................................................................................... 26
Write to Write Command Interval ....................................................................................................... 26
Write to Read Command Interval ....................................................................................................... 27
Read to Write Command Interval ....................................................................................................... 28
Burst Stop Command ......................................................................................................................... 29
Precharge Termination ....................................................................................................................... 30
12.2.1
12.2.2
Precharge Termination in READ Cycle ................................................................................... 30
Precharge Termination in WRITE Cycle ................................................................................. 31
Data Sheet E0344N10 (Ver. 1.0)
CONTENTS
PD45128163