UPD45128163-A75L ELPIDA [Elpida Memory], UPD45128163-A75L Datasheet - Page 24

• Manufacturer Part Number: UPD45128163-A75L
• Description: 128M-bit Synchronous DRAM 4-bank, LVTTL
• Manufacturer: ELPIDA [Elpida Memory]

10. Auto Precharge
Write command (Read with Auto precharge command or Write with Auto precharge command), auto precharge is
selected and begins automatically.
next activate command to the bank being precharged cannot be executed until the precharge cycle ends.
satisfied.
register and whether read or write cycle.
10.1 Read with Auto Precharge
latency of 3) the last data word output.
Remark READA means Read with Auto precharge
24
/CAS latency = 2
/CAS latency = 3
During a read or write command cycle, A10 controls whether auto precharge is selected. A10 high in the Read or
The t
In read cycle, once auto precharge has started, an activate command to the bank can be issued after t
In write cycle, the t
The timing that begins the auto precharge cycle depends on both the /CAS latency programmed into the mode
During a read cycle, the auto precharge begins one clock earlier (/CAS latency of 2) or two clocks earlier (/CAS
RAS
Command
Command
CLK
DQ
DQ
must be satisfied with a read with auto precharge or a write with auto precharge operation. In addition, the
DAL
T0
must be satisfied to issue the next activate command to the bank being precharged.
READA B
READA B
T1
T2
Data Sheet E0344N10 (Ver. 1.0)
QB1
T3
QB2
QB1
T4
Auto precharge starts
Auto precharge starts
QB3
QB2
T5
QB4
QB3
T6
QB4
T7
(t
RAS
PD45128163
T8
Burst length = 4
must be satisfied)
RP
Hi-Z
has been
Hi-Z
T9