UPD45128163-A75L ELPIDA [Elpida Memory], UPD45128163-A75L Datasheet - Page 18

• Manufacturer Part Number: UPD45128163-A75L
• Description: 128M-bit Synchronous DRAM 4-bank, LVTTL
• Manufacturer: ELPIDA [Elpida Memory]

5. Initialization
(1)
(2)
(3)
(4)
Remarks 1. The sequence of Mode register programming and Refresh above may be transposed.
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The synchronous DRAM is initialized in the power-on sequence according to the following.
To stabilize internal circuits, when power is applied, a 100 s or longer pause must precede any signal toggling.
After the pause, all banks must be precharged using the Precharge command (The Precharge all banks
command is convenient).
Once the precharge is completed and the minimum t
After the mode register set cycle, t
Two or more CBR (Auto) refresh must be performed.
2. CKE and DQM must be held high until the Precharge command is issued to ensure data-bus Hi-Z.
RSC
(2 CLK minimum) pause must be satisfied as well.
Data Sheet E0344N10 (Ver. 1.0)
RP
is satisfied, the mode register can be programmed.
PD45128163