UPD45128163-A75L ELPIDA [Elpida Memory], UPD45128163-A75L Datasheet - Page 7

• Manufacturer Part Number: UPD45128163-A75L
• Description: 128M-bit Synchronous DRAM 4-bank, LVTTL
• Manufacturer: ELPIDA [Elpida Memory]

13. Electrical Specifications ................................................................................................................. 32
14. Package Drawing ............................................................................................................................ 83
15. Recommended Soldering Conditions ........................................................................................... 84
13.1
13.2
13.3
13.4
13.5
13.6
13.7
13.8
13.9
13.10 CBR (Auto) Refresh ............................................................................................................................. 49
13.11 Self Refresh (Entry and Exit) .............................................................................................................. 50
13.12 Random Column Read (Page with Same Bank) ............................................................................... 51
13.13 Random Column Write (Page with Same Bank) ............................................................................... 53
13.14 Random Row Read (Ping-Pong Banks) ............................................................................................ 55
13.15 Random Row Write (Ping-Pong Banks) ............................................................................................ 57
13.16 Read and Write .................................................................................................................................... 59
13.17 Interleaved Column Read Cycle ......................................................................................................... 61
13.18 Interleaved Column Write Cycle ........................................................................................................ 63
13.19 Auto Precharge after Read Burst ....................................................................................................... 65
13.20 Auto Precharge after Write Burst ...................................................................................................... 67
13.21 Full Page Read Cycle .......................................................................................................................... 69
13.22 Full Page Write Cycle .......................................................................................................................... 71
13.23 Byte Write Operation ........................................................................................................................... 73
13.24 Burst Read and Single Write (Option) ............................................................................................... 75
13.25 Full Page Random Column Read ....................................................................................................... 77
13.26 Full Page Random Column Write ...................................................................................................... 79
13.27 PRE (Precharge) Termination of Burst .............................................................................................. 81
AC Parameters for Read Timing ........................................................................................................ 37
AC Parameters for Write Timing ........................................................................................................ 39
Relationship between Frequency and Latency ................................................................................ 40
Mode Register Set ............................................................................................................................... 41
Power on Sequence and CBR (Auto) Refresh .................................................................................. 42
/CS Function ........................................................................................................................................ 43
Clock Suspension during Burst Read (using CKE Function) ......................................................... 44
Clock Suspension during Burst Write (using CKE Function) ......................................................... 46
Power Down Mode and Clock Mask .................................................................................................. 48
Data Sheet E0344N10 (Ver. 1.0)
PD45128163
7