UPD45128163-A75L ELPIDA [Elpida Memory], UPD45128163-A75L Datasheet - Page 26

• Manufacturer Part Number: UPD45128163-A75L
• Description: 128M-bit Synchronous DRAM 4-bank, LVTTL
• Manufacturer: ELPIDA [Elpida Memory]

11. Read / Write Command Interval
11.1 Read to Read Command Interval
read operation does not completed. READ will be interrupted by another READ.
without any restriction.
Command
11.2 Write to Write Command Interval
begin with a new Write command. WRITE will be interrupted by another WRITE.
without any restriction.
26
Command
During a read cycle, when new Read command is issued, it will be effective after /CAS latency, even if the previous
The interval between the commands is 1 cycle minimum. Each Read command can be issued in every clock
During a write cycle, when a new Write command is issued, the previous burst will terminate and the new burst will
The interval between the commands is minimum 1 cycle. Each Write command can be issued in every clock
CLK
DQ
CLK
DQ
T0
T0
WRITE A
READ A
DA1
T1
T1
1cycle
1cycle
READ B
WRITE B
DB1
T2
T2
QA1
Data Sheet E0344N10 (Ver. 1.0)
DB2
T3
T3
QB1
DB3
T4
T4
QB2
DB4
T5
T5
QB3
T6
T6
Burst length = 4, /CAS latency = 2
Hi-Z
Burst length = 4, /CAS latency = 2
QB4
T7
T7
T8
PD45128163
T8
T9
Hi-Z