UPD45128163-A75L ELPIDA [Elpida Memory], UPD45128163-A75L Datasheet - Page 35

• Manufacturer Part Number: UPD45128163-A75L
• Description: 128M-bit Synchronous DRAM 4-bank, LVTTL
• Manufacturer: ELPIDA [Elpida Memory]

Synchronous Characteristics
Note 1. Output load
Clock cycle time
Access time from CLK
CLK high level width
CLK low level width
Data-out hold time
Data-out low-impedance time
Data-out high-impedance time /CAS latency = 3
Data-in setup time
Data-in hold time
Address setup time
Address hold time
CKE setup time
CKE hold time
CKE setup time (Power down exit)
Command (/CS, /RAS, /CAS, /WE, DQM)
setup time
Command (/CS, /RAS, /CAS, /WE, DQM)
hold time
Parameter
/CAS latency = 3
/CAS latency = 2
/CAS latency = 3
/CAS latency = 2
/CAS latency = 2
Symbol
t
t
t
t
t
t
t
t
t
t
t
CKSP
t
t
t
t
t
t
t
t
CKS
CKH
CMS
CMH
CK3
CK2
AC3
AC2
HZ3
HZ2
CH
OH
DS
DH
AS
AH
CL
LZ
Data Sheet E0344N10 (Ver. 1.0)
MIN.
7.5
7.5
2.5
2.5
1.5
0.8
1.5
0.8
1.5
0.8
1.5
1.5
0.8
3
0
3
3
-A 75A
(133 MHz)
(133 MHz)
MAX.
5.4
5.4
5.4
5.4
MIN.
7.5
2.5
2.5
1.5
0.8
1.5
0.8
1.5
0.8
1.5
1.5
0.8
10
3
0
3
3
-A 75
(133 MHz)
(100 MHz)
MAX.
5.4
5.4
6
6
MIN.
10
8
3
3
3
0
3
3
2
1
2
1
2
1
2
2
1
-A 80
(125 MHz)
(100 MHz)
MAX.
6
6
6
6
MIN.
10
13
3
3
3
0
3
3
2
1
2
1
2
1
2
2
1
-A 10
(100 MHz)
(77 MHz)
MAX.
6
7
6
7
PD45128163
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note
1
1
1
35