UPD45128163-A75L ELPIDA [Elpida Memory], UPD45128163-A75L Datasheet - Page 13

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UPD45128163-A75L

Manufacturer Part Number
UPD45128163-A75L
Description
128M-bit Synchronous DRAM 4-bank, LVTTL
Manufacturer
ELPIDA [Elpida Memory]
Datasheet
4. Truth Table
4.1 Command Truth Table
Remark H = High level, L = Low level,
4.2 DQM Truth Table
Remark H = High level, L = Low level,
4.3 CKE Truth Table
Remark H = High level, L = Low level,
Device deselect
No operation
Burst stop
Read
Read with auto precharge
Write
Write with auto precharge
Bank activate
Precharge select bank
Precharge all banks
Mode register set
Upper byte write enable / output enable
Lower byte write enable / output enable
Upper byte write inhibit / output disable
Lower byte write inhibit / output disable
Activating
Any
Clock suspend
Idle
Idle
Self refresh
Idle
Power down
Current state
Function
Function
Clock suspend mode entry
Clock suspend mode
Clock suspend mode exit
CBR (auto) refresh command
Self refresh entry
Self refresh exit
Power down entry
Power down exit
Function
DESL
NOP
BST
READ
READA
WRIT
WRITA
ACT
PRE
PALL
MRS
Symbol
= High or Low level (Don't care)
= High or Low level (Don't care)
= High or Low level (Don't care), V = Valid data input
ENBU
ENBL
MASKU
MASKL
n – 1
Symbol
H
H
H
H
H
H
H
H
H
H
H
Data Sheet E0344N10 (Ver. 1.0)
CKE
REF
SELF
Symbol
n
n – 1
H
H
H
H
CKE
n – 1
/CS
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
n
CKE
/RAS
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
n
L
L
L
L
U
H
L
DQM
/CAS
/CS
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
H
L
L
/RAS
/WE
H
H
H
H
H
H
L
L
L
L
L
L
L
L
/CAS
BA1,
BA0
V
V
V
V
V
V
H
H
L
L
L
PD45128163
/WE
A10
H
H
V
H
H
H
H
H
L
L
L
L
Address
A9 - A0
A11,
V
V
V
V
V
V
13

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