UPD45128163-A75L ELPIDA [Elpida Memory], UPD45128163-A75L Datasheet - Page 27

• Manufacturer Part Number: UPD45128163-A75L
• Description: 128M-bit Synchronous DRAM 4-bank, LVTTL
• Manufacturer: ELPIDA [Elpida Memory]

11.3 Write to Read Command Interval
/CAS latency = 2
/CAS latency = 3
Write command and Read command interval is also 1 cycle.
Only the write data before Read command will be written.
The data bus must be Hi-Z at least one cycle prior to the first D
Command
Command
CLK
DQ
DQ
T0
WRITE A
WRITE A
DA1
DA1
T1
READ B
READ B
T2
Data Sheet E0344N10 (Ver. 1.0)
Hi-Z
Hi-Z
T3
QB1
OUT
T4
.
QB2
QB1
T5
QB3
QB2
T6
QB4
QB3
T7
PD45128163
Burst length = 4
QB4
T8
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