UPD45128163-A75L ELPIDA [Elpida Memory], UPD45128163-A75L Datasheet - Page 19

• Manufacturer Part Number: UPD45128163-A75L
• Description: 128M-bit Synchronous DRAM 4-bank, LVTTL
• Manufacturer: ELPIDA [Elpida Memory]

6. Programming the Mode Register
and BA1(A12) as data inputs. The register retains data until it is reprogrammed or the device loses power.
before the data will be available.
between Frequency and Latency shows the relationship of /CAS latency to the clock period and the speed grade of
the device.
completed, the output bus will become Hi-Z.
“Sequential” or “Interleave”. The method chosen will depend on the type of CPU in the system.
addressing. 7.1 Burst Length and Sequence shows the addressing sequence for each burst length using them.
Both sequences support bursts of 1, 2, 4 and 8. Additionally, sequence supports the full page length.
The mode register is programmed by the Mode register set command using address bits A11 through A0, BA0(A13)
The mode register has four fields;
Options
/CAS latency : A6 through A4
Wrap type
Burst length
Following mode register programming, no command can be issued before at least 2 CLK have elapsed.
/CAS Latency
/CAS latency is the most critical of the parameters being set. It tells the device how many clocks must elapse
The value is determined by the frequency of the clock and the speed grade of the device. 13.3 Relationship
Burst Length
Burst Length is the number of words that will be output or input in a read or write cycle. After a read burst is
The burst length is programmable as 1, 2, 4, 8 or full page.
Wrap Type (Burst Sequence)
The wrap type specifies the order in which the burst data will be addressed. This order is programmable as either
Some microprocessor cache systems are optimized for sequential addressing and others for interleaved
: A11 through A7, BA0(A13), BA1(A12)
: A3
: A2 through A0
Data Sheet E0344N10 (Ver. 1.0)
PD45128163
19