UPD45128163-A75L ELPIDA [Elpida Memory], UPD45128163-A75L Datasheet - Page 23

• Manufacturer Part Number: UPD45128163-A75L
• Description: 128M-bit Synchronous DRAM 4-bank, LVTTL
• Manufacturer: ELPIDA [Elpida Memory]

9. Precharge
the idle state after t
as follows.
(MIN.)
calculated by dividing t
valid. In the following table, minus means clocks before the reference; plus means time after the reference.
The precharge command can be issued anytime after t
Soon after the precharge command is issued, precharge operation performed and the synchronous DRAM enters
The earliest timing in a read cycle that a precharge command can be issued without losing any data in the burst is
It is depending on the /CAS latency and clock cycle time.
In summary, the precharge command can be issued relative to reference clock that indicates the last data word is
In order to write all data to the memory cell correctly, the asynchronous parameter “t
specification defines the earliest time that a precharge command can be issued. Minimum number of clocks is
/CAS latency = 3
/CAS latency = 2
/CAS latency
Command
Command
2
3
RP
is satisfied. The parameter t
CLK
DPL (MIN.)
DQ
DQ
with clock cycle time.
T0
READ
READ
T1
Data Sheet E0344N10 (Ver. 1.0)
T2
RP
is the time required to perform the precharge.
RAS (MIN.)
Q1
Read
T3
–1
–2
is satisfied.
Q2
Q1
T4
PRE
PRE
Q2
Q3
T5
Q3
Q4
T6
DPL
(t
” must be satisfied. The t
RAS
Q4
T7
must be satisfied)
+t
+t
Write
Burst length=4
DPL (MIN.)
DPL (MIN.)
T8
PD45128163
Hi-Z
Hi-Z
DPL
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