UPD75238GJ NEC [NEC], UPD75238GJ Datasheet - Page 180
UPD75238GJ
Manufacturer Part Number
UPD75238GJ
Description
4 BIT SINGLE-CHIP MICROCOMPUTER
Manufacturer
NEC [NEC]
Datasheet
1.UPD75238GJ.pdf
(190 pages)
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180
DATA HOLD CHARACTERISTICS BY LOW SUPPLY VOLTAGE IN DATA MEMORY STOP MODE
(T
Data Hold Timing (STOP Mode Release by RESET)
RESET
Data Hold Timing (Standby Release Signal: STOP Mode Release by Interrupt Signal)
Data hold supply voltage
Data hold supply current
Release signal setting time
Oscillation stability wait
time
a
Standby release signal
(interrupt request)
V
Notes 1. Excluding the current which flows through the built-in pull-up or pull-down resistors
V
= -40 to +85 C)
DD
DD
Note 2
Parameter
2. CPU operation stop time for preventing unstable operation at the beginning of oscillation
3. This value depends on the settings of the basic interval timer mode register (BTM) shown below.
STOP instruction execution
STOP instruction execution
BTM3
—
—
—
—
Note 1
BTM2
0
0
1
1
Symbol
V
I
t
t
DDDR
SREL
WAIT
DDDR
BTM1
0
1
0
1
Min.
2.0
0
STOP mode
STOP mode
V
V
BTM0
DDDR
DDDR
Data hold mode
Data hold mode
0
1
1
1
Note 3
2
Typ.
0.1
17
/f
X
2
2
2
2
20
17
15
13
/f
/f
/f
/f
X
X
X
X
Max.
(approx. 175 ms)
(approx. 21.8 ms)
(approx. 5.46 ms)
(approx. 1.37 ms)
f
6.0
10
X
= 6.0 MHz
Internal reset operation
Unit
ms
ms
V
A
s
Wait time
t
t
SREL
SREL
V
Release by RESET
Release by interrupt request
DDDR
2
2
2
2
20
17
15
13
HALT mode
HALT mode
/f
/f
/f
/f
= 2.0 V
X
X
X
X
t
t
WAIT
f
WAIT
(approx. 250 ms)
(approx. 31.3 ms)
(approx. 7.82 ms)
(approx. 1.95 ms)
X
= 4.19 MHz
Conditions
Operation
mode
Operation
mode
PD75238
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