LCMXO2-2000HC-4FTG256C Lattice, LCMXO2-2000HC-4FTG256C Datasheet - Page 102

• Manufacturer Part Number: LCMXO2-2000HC-4FTG256C
• Description: FPGA - Field Programmable Gate Array 2112 LUTs 207 IO 3.3V 4 Spd
• Manufacturer: Lattice

Specifications of LCMXO2-2000HC-4FTG256C

• Rohs: yes
• Number Of Gates: 2 K
• Embedded Block Ram - Ebr: 74 Kbit
• Number Of I/os: 207
• Maximum Operating Frequency: 269 MHz
• Operating Supply Voltage: 1.14 V to 3.465 V, 2.375 V to 3.465 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: ftBGA-256
• Distributed Ram: 16 Kbit
• Minimum Operating Temperature: 0 C
• Operating Supply Current: 4.8 mA
• Factory Pack Quantity: 90
• User Flash Memory - Ufm: 80 Kbit

R1 Device Specifications
The LCMXO2-1200ZE/HC “R1” devices have the same specifications as their Standard (non-R1) counterparts
except as listed below. For more details on the R1 to Standard migration refer to AN8086,
from MachXO2-1200-R1 to Standard Non-R1)
• The User Flash Memory (UFM) cannot be programmed through the internal WISHBONE interface. It can still be
• The on-chip differential input termination resistor value is higher than intended. It is approximately 200 as
• Soft Error Detection logic may not produce the correct result when it is run for the first time after configuration. To
• Under certain conditions, IIH exceeds data sheet specifications. The following table provides more details:
• The user SPI interface does not operate correctly in some situations. During master read access and slave write
• In GDDRX2, GDDRX4 and GDDR71 modes, ECLKSYNC may have a glitch in the output under certain condi-
• When using the hard I
• PLL Lock signal will glitch high when coming out of standby. This glitch lasts for about 10
• Dual boot only available on HC devices, requires tying VCC and VCCIO2 to the same 3.3V or 2.5V supply.
VPAD > VCCIO
VPAD = VCCIO
VPAD = VCCIO
VPAD < VCCIO
programmed through the JTAG/SPI/I
opposed to the intended 100. It is recommended to use external termination resistors for differential inputs. The
on-chip termination resistors can be disabled through Lattice design software.
use this feature, discard the result from the first operation. Subsequent operations will produce the correct result.
access, the last byte received does not generate the RRDY interrupt.
tions, leading to possible loss of synchronization.
low.
Condition
2
C IP core, the I
Clamp
OFF
OFF
OFF
ON
2
C ports.
2
C status registers I2C_1_SR and I2C_2_SR may not update correctly.
Pad Rising
IIH Max.
10µA
10µA
1mA
1mA
Devices.
5-18
Pad Falling
IIH Min.
-10µA
-10µA
-1mA
-1mA
Steady State Pad
MachXO2 Family Data Sheet
High IIH
10µA
10µA
1mA
1mA
Ordering Information
µ
Designing for Migration
sec before returning
Steady State Pad
Low IIL
10µA
10µA
10µA
10µA