LCMXO2-2000HC-4FTG256C Lattice, LCMXO2-2000HC-4FTG256C Datasheet - Page 12

• Manufacturer Part Number: LCMXO2-2000HC-4FTG256C
• Description: FPGA - Field Programmable Gate Array 2112 LUTs 207 IO 3.3V 4 Spd
• Manufacturer: Lattice

Specifications of LCMXO2-2000HC-4FTG256C

• Rohs: yes
• Number Of Gates: 2 K
• Embedded Block Ram - Ebr: 74 Kbit
• Number Of I/os: 207
• Maximum Operating Frequency: 269 MHz
• Operating Supply Voltage: 1.14 V to 3.465 V, 2.375 V to 3.465 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: ftBGA-256
• Distributed Ram: 16 Kbit
• Minimum Operating Temperature: 0 C
• Operating Supply Current: 4.8 mA
• Factory Pack Quantity: 90
• User Flash Memory - Ufm: 80 Kbit

The LOCK signal is asserted when the PLL determines it has achieved lock and de-asserted if a loss of lock is
detected. A block diagram of the PLL is shown in Figure 2-7.
The setup and hold times of the device can be improved by programming a phase shift into the CLKOS, CLKOS2,
and CLKOS3 output clocks which will advance or delay the output clock with reference to the CLKOP output clock.
This phase shift can be either programmed during configuration or can be adjusted dynamically. In dynamic mode,
the PLL may lose lock after a phase adjustment on the output used as the feedback source and not relock until the
t
The MachXO2 also has a feature that allows the user to select between two different reference clock sources
dynamically. This feature is implemented using the PLLREFCS primitive. The timing parameters for the PLL are
shown in the table.
The MachXO2 PLL contains a WISHBONE port feature that allows the PLL settings, including divider values, to be
dynamically changed from the user logic. When using this feature the EFB block must also be instantiated in the
design to allow access to the WISHBONE ports. Similar to the dynamic phase adjustment, when PLL settings are
updated through the WISHBONE port the PLL may lose lock and not relock until the t
isfied. The timing parameters for the PLL are shown in the table.
For more details on the PLL and the WISHBONE interface, see TN1199,
Usage
Figure 2-7. PLL Diagram
LOCK
CLKFB
CLKI
parameter has been satisfied.
Guide.
PHASESEL[1:0]
PHASESTEP
PHASEDIR
FBKSEL
RST, RESETM, RESETC, RESETD
ENCLKOP, ENCLKOS, ENCLKOS2, ENCLKOS3
PLLCLK, PLLRST, PLLSTB, PLLWE, PLLDATI[7:0], PLLADDR[4:0]
STDBY
M (1 - 40)
REFCLK
Divider
N (1 - 40)
FBKCLK
Divider
Dynamic
Phase
Adjust
REFCLK
Internal Feedback
CLKOP, CLKOS, CLKOS2, CLKOS3
Fractional-N
Synthesizer
Phase detector,
VCO, and
loop filter.
4
2-8
A0
B0
C0
D0
Mux
D1
CLKOS2
(1 - 128)
(1 - 128)
(1 - 128)
CLKOP
CLKOS
Divider
Divider
Divider
CLKOS3
(1 - 128)
Divider
Edge Trim
Edge Trim
MachXO2 sysCLOCK PLL Design and
Adjust/
Phase
Adjust/
Phase
Phase
Adjust
MachXO2 Family Data Sheet
Phase
Adjust
PLLDATO[7:0] , PLLACK
LOCK
Mux
Mux
Mux
Mux
A2
B2
C2
D2
parameter has been sat-
Detect
Lock
Synch
Synch
Synch
Synch
ClkEn
ClkEn
ClkEn
ClkEn
Architecture
DPHSRC
CLKOS2
CLKOS3
CLKOP
CLKOS
LOCK