LCMXO2-2000HC-4FTG256C Lattice, LCMXO2-2000HC-4FTG256C Datasheet - Page 13

• Manufacturer Part Number: LCMXO2-2000HC-4FTG256C
• Description: FPGA - Field Programmable Gate Array 2112 LUTs 207 IO 3.3V 4 Spd
• Manufacturer: Lattice

Specifications of LCMXO2-2000HC-4FTG256C

• Rohs: yes
• Number Of Gates: 2 K
• Embedded Block Ram - Ebr: 74 Kbit
• Number Of I/os: 207
• Maximum Operating Frequency: 269 MHz
• Operating Supply Voltage: 1.14 V to 3.465 V, 2.375 V to 3.465 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: ftBGA-256
• Distributed Ram: 16 Kbit
• Minimum Operating Temperature: 0 C
• Operating Supply Current: 4.8 mA
• Factory Pack Quantity: 90
• User Flash Memory - Ufm: 80 Kbit

Table 2-4 provides signal descriptions of the PLL block.
sysMEM Embedded Block RAM Memory
The MachXO2-640/U and larger devices contain sysMEM Embedded Block RAMs (EBRs). The EBR consists of a
9-Kbit RAM, with dedicated input and output registers. This memory can be used for a wide variety of purposes
including data buffering, PROM for the soft processor and FIFO.
sysMEM Memory Block
The sysMEM block can implement single port, dual port, pseudo dual port, or FIFO memories. Each block can be
used in a variety of depths and widths as shown in Table 2-5.
Table 2-4. PLL Signal Descriptions
CLKI
CLKFB
PHASESEL[1:0]
PHASEDIR
PHASESTEP
CLKOP
CLKOS
CLKOS2
CLKOS3
LOCK
DPHSRC
STDBY
RST
RESETM
RESETC
RESETD
ENCLKOP
ENCLKOS
ENCLKOS2
ENCLKOS3
PLLCLK
PLLRST
PLLSTB
PLLWE
PLLADDR [4:0]
PLLDATI [7:0]
PLLDATO [7:0]
PLLACK
Port Name
I/O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Input clock to PLL
Feedback clock
Select which output is affected by Dynamic Phase adjustment ports
Dynamic Phase adjustment direction
Dynamic Phase step – toggle shifts VCO phase adjust by one step.
Primary PLL output clock (with phase shift adjustment)
Secondary PLL output clock (with phase shift adjust)
Secondary PLL output clock2 (with phase shift adjust)
Secondary PLL output clock3 (with phase shift adjust)
PLL LOCK, asynchronous signal. Active high indicates PLL is locked to input and feed-
back signals.
Dynamic Phase source – ports or
Standby signal to power down the PLL
PLL reset without resetting the M-divider. Active high reset.
PLL reset - includes resetting the M-divider. Active high reset.
Reset for CLKOS2 output divider only. Active high reset.
Reset for CLKOS3 output divider only. Active high reset.
Enable PLL output CLKOP
Enable PLL output CLKOS when port is active
Enable PLL output CLKOS2 when port is active
Enable PLL output CLKOS3 when port is active
PLL data bus clock input signal
PLL data bus reset. This resets only the data bus not any register values.
PLL data bus strobe signal
PLL data bus write enable signal
PLL data bus data input
PLL data bus data output
PLL data bus acknowledge signal
PLL data bus address
2-9
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Architecture