LCMXO2-2000HC-4FTG256C Lattice, LCMXO2-2000HC-4FTG256C Datasheet - Page 15

• Manufacturer Part Number: LCMXO2-2000HC-4FTG256C
• Description: FPGA - Field Programmable Gate Array 2112 LUTs 207 IO 3.3V 4 Spd
• Manufacturer: Lattice

Specifications of LCMXO2-2000HC-4FTG256C

• Rohs: yes
• Number Of Gates: 2 K
• Embedded Block Ram - Ebr: 74 Kbit
• Number Of I/os: 207
• Maximum Operating Frequency: 269 MHz
• Operating Supply Voltage: 1.14 V to 3.465 V, 2.375 V to 3.465 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: ftBGA-256
• Distributed Ram: 16 Kbit
• Minimum Operating Temperature: 0 C
• Operating Supply Current: 4.8 mA
• Factory Pack Quantity: 90
• User Flash Memory - Ufm: 80 Kbit

Figure 2-8. sysMEM Memory Primitives
Table 2-6. EBR Signal Descriptions
AD[12:0]
DI[8:0]
CS[2:0]
OCE
RST
CLK
WE
CE
CLK
CE
OCE
RST
BE
WE
AD
DI
DO
CS
AFF
FF
AEF
EF
RPRST
1. Optional signals.
2. For dual port EBR primitives a trailing ‘A’ or ‘B’ in the signal name specifies the EBR port A or port B respectively.
3. For FIFO RAM mode primitive, a trailing ‘R’ or ‘W’ in the signal name specifies the FIFO read port or write port respec-
4. For FIFO RAM mode primitive FULLI has the same function as CSW(2) and EMPTYI has the same function as CSR(2).
5. In FIFO mode, CLKW is the write port clock, CSW is the write port chip select, CLKR is the read port clock, CSR is the
tively.
read port chip select, ORE is the output read enable.
Single-Port RAM
1
1
Port Name
EBR
CSW[1:0]
DI[17:0]
CLKW
FULLI
RST
WE
DO[8:0]
Clock
Clock Enable
Output Clock Enable
Reset
Byte Enable
Write Enable
Address Bus
Data In
Data Out
Chip Select
FIFO RAM Almost Full Flag
FIFO RAM Full Flag
FIFO RAM Almost Empty Flag
FIFO RAM Empty Flag
FIFO RAM Read Pointer Reset
FIFO RAM
EBR
ADA[12:0]
DOA[8:0]
CSA[2:0]
DIA[8:0]
OCEA
RSTA
CLKA
WEA
CEA
Description
True Dual Port RAM
AFF
FF
AEF
EF
DO[17:0]
ORE
CLKR
RE
EMPTYI
CSR[1:0]
RPRST
EBR
2-11
AD[12:0]
CS[2:0]
OCE
CLK
RST
CE
DI[8:0]
ADB[12:0]
CLKB
CEB
RSTB
WEB
CSB[2:0]
OCEB
DOB[8:0]
ROM
EBR
ADW[8:0]
CSW[2:0]
MachXO2 Family Data Sheet
DI[17:0]
Rising Clock Edge
BE[1:0]
CLKW
CEW
RST
Active State
Active High
Active High
Active High
Active High
Active High
Active High
Pseudo Dual Port RAM
—
—
—
—
—
—
—
—
DO[17:0]
EBR
Architecture
ADR[12:0]
CLKR
CER
DO[17:0]
OCER
CSR[2:0]