LCMXO2-2000HC-4FTG256C Lattice, LCMXO2-2000HC-4FTG256C Datasheet - Page 67

• Manufacturer Part Number: LCMXO2-2000HC-4FTG256C
• Description: FPGA - Field Programmable Gate Array 2112 LUTs 207 IO 3.3V 4 Spd
• Manufacturer: Lattice

Specifications of LCMXO2-2000HC-4FTG256C

• Rohs: yes
• Number Of Gates: 2 K
• Embedded Block Ram - Ebr: 74 Kbit
• Number Of I/os: 207
• Maximum Operating Frequency: 269 MHz
• Operating Supply Voltage: 1.14 V to 3.465 V, 2.375 V to 3.465 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: ftBGA-256
• Distributed Ram: 16 Kbit
• Minimum Operating Temperature: 0 C
• Operating Supply Current: 4.8 mA
• Factory Pack Quantity: 90
• User Flash Memory - Ufm: 80 Kbit

LPDDR
t
t
t
t
f
f
f
DDR
t
t
t
t
f
f
f
DDR2
t
t
t
t
f
f
f
1. Exact performance may vary with device and design implementation. Commercial timing numbers are shown at 85°C and 1.14V. Other
2. General I/O timing numbers based on LVCMOS 2.5, 8mA, 0pf load.
3. Generic DDR timing numbers based on LVDS I/O (for input, output, and clock ports).
4. DDR timing numbers based on SSTL25. DDR2 timing numbers based on SSTL18. LPDDR timing numbers based in LVCMOS18.
5. 7:1 LVDS (GDDR71) uses the LVDS I/O standard (for input, output, and clock ports).
6. For Generic DDRX1 mode t
7. The t
8. This number for general purpose usage. Duty cycle tolerance is +/-10%.
9. Duty cycle is +/- 5% for system usage.
10. The above timing numbers are generated using the Diamond design tool. Exact performance may vary with the device selected.
DVADQ
DVEDQ
DQVBS
DQVAS
DATA
SCLK
LPDDR
DVADQ
DVEDQ
DQVBS
DQVAS
DATA
SCLK
MEM_DDR
DVADQ
DVEDQ
DQVBS
DQVAS
DATA
SCLK
MEM_DDR2
Parameter
operating conditions, including industrial, can be extracted from the Diamond software.
9
9
9
SU_DEL
Input Data Valid After DQS
Input
Input Data Hold After DQS
Input
Output Data Invalid Before
DQS Output
Output Data Invalid After DQS
Output
MEM LPDDR Serial Data
Speed
SCLK Frequency
LPDDR Data Transfer Rate
Input Data Valid After DQS
Input
Input Data Hold After DQS
Input
Output Data Invalid Before
DQS Output
Output Data Invalid After DQS
Output
MEM DDR Serial Data Speed
SCLK Frequency
MEM DDR Data Transfer Rate
Input Data Valid After DQS
Input
Input Data Hold After DQS
Input
Output Data Invalid Before
DQS Output
Output Data Invalid After DQS
Output
MEM DDR Serial Data Speed
SCLK Frequency
MEM DDR2 Data Transfer
Rate
and t
H_DEL
Description
values use the SCLK_ZERHOLD default step size. Each step is 167ps (-3), 182ps (-2), 195ps (-1).
SU
= t
HO
= (t
DVE
- t
DVA
MachXO2-1200/U
and larger devices,
right side only.
MachXO2-1200/U
and larger devices,
right side only.
MachXO2-1200/U
and larger devices,
right side only.
- 0.03ns)/2.
Device
3-28
0.665
0.665
0.690
Min.
0.25
0.25
0.25
0.25
0.25
0.25
N/A
N/A
—
—
—
—
—
—
—
—
—
0
-3
DC and Switching Characteristics
0.349
0.347
0.372
Max.
120
120
140
140
140
140
—
—
—
60
—
—
—
70
—
—
—
70
MachXO2 Family Data Sheet
0.630
0.637
0.658
Min.
0.25
0.25
0.25
0.25
0.25
0.25
N/A
N/A
—
—
—
—
—
—
—
—
—
0
-2
0.381
0.374
0.394
Max.
110
110
116
116
116
116
55
58
58
—
—
—
—
—
—
—
—
—
0.613
0.616
0.618
Min.
0.25
0.25
0.25
0.25
0.25
0.25
N/A
N/A
—
—
—
—
—
—
—
—
—
0
-1
0.396
0.393
0.410
Max.
96
48
96
98
49
98
98
49
98
—
—
—
—
—
—
—
—
—
Units
Mbps
Mbps
Mbps
Mbps
Mbps
Mbps
MHz
MHz
MHz
UI
UI
UI
UI
UI
UI
UI
UI
UI
UI
UI
UI