LCMXO2-2000HC-4FTG256C Lattice, LCMXO2-2000HC-4FTG256C Datasheet - Page 9

• Manufacturer Part Number: LCMXO2-2000HC-4FTG256C
• Description: FPGA - Field Programmable Gate Array 2112 LUTs 207 IO 3.3V 4 Spd
• Manufacturer: Lattice

Specifications of LCMXO2-2000HC-4FTG256C

• Rohs: yes
• Number Of Gates: 2 K
• Embedded Block Ram - Ebr: 74 Kbit
• Number Of I/os: 207
• Maximum Operating Frequency: 269 MHz
• Operating Supply Voltage: 1.14 V to 3.465 V, 2.375 V to 3.465 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: ftBGA-256
• Distributed Ram: 16 Kbit
• Minimum Operating Temperature: 0 C
• Operating Supply Current: 4.8 mA
• Factory Pack Quantity: 90
• User Flash Memory - Ufm: 80 Kbit

Ripple mode includes an optional configuration that performs arithmetic using fast carry chain methods. In this con-
figuration (also referred to as CCU2 mode) two additional signals, Carry Generate and Carry Propagate, are gener-
ated on a per-slice basis to allow fast arithmetic functions to be constructed by concatenating slices.
RAM Mode
In this mode, a 16x4-bit distributed single port RAM (SPR) can be constructed by using each LUT block in Slice 0
and Slice 1 as a 16x1-bit memory. Slice 2 is used to provide memory address and control signals. A 16x2-bit
Pseudo Dual Port RAM (PDPR) memory is created by using one slice as the read-write port and the other compan-
ion slice as the read-only port.
MachXO2 devices support distributed memory initialization.
The Lattice design tools support the creation of a variety of different size memories. Where appropriate, the soft-
ware will construct these using distributed memory primitives that represent the capabilities of the PFU. Table 2-3
shows the number of slices required to implement different distributed RAM primitives. For more information about
using RAM in MachXO2 devices, please see TN1201,
Table 2-3. Number of Slices Required For Implementing Distributed RAM
ROM Mode
ROM mode uses the LUT logic; hence, slices 0-3 can be used in ROM mode. Preloading is accomplished through
the programming interface during PFU configuration.
For more information on the RAM and ROM modes, please refer to TN1201,
Devices.
Routing
There are many resources provided in the MachXO2 devices to route signals individually or as buses with related
control signals. The routing resources consist of switching circuitry, buffers and metal interconnect (routing) seg-
ments.
The inter-PFU connections are made with three different types of routing resources: x1 (spans two PFUs), x2
(spans three PFUs) and x6 (spans seven PFUs). The x1, x2, and x6 connections provide fast and efficient connec-
tions in the horizontal and vertical directions.
The design tools take the output of the synthesis tool and places and routes the design. Generally, the place and
route tool is completely automatic, although an interactive routing editor is available to optimize the design.
Clock/Control Distribution Network
Each MachXO2 device has eight clock inputs (PCLK [T, C] [Banknum]_[2..0]) – three pins on the left side, two pins
each on the bottom and top sides and one pin on the right side. These clock inputs drive the clock nets. These
eight inputs can be differential or single-ended and may be used as general purpose I/O if they are not used to
drive the clock nets. When using a single ended clock input, only the PCLKT input can drive the clock tree directly.
The MachXO2 architecture has three types of clocking resources: edge clocks, primary clocks and secondary high
fanout nets. MachXO2-640U, MachXO2-1200/U and higher density devices have two edge clocks each on the top
and bottom edges. Lower density devices have no edge clocks. Edge clocks are used to clock I/O registers and
have low injection time and skew. Edge clock inputs are from PLL outputs, primary clock pads, edge clock bridge
outputs and CIB sources.
Number of slices
Note: SPR = Single Port RAM, PDPR = Pseudo Dual Port RAM
Memory Usage Guide for MachXO2
2-5
SPR 16x4
3
PDPR 16x4
3
MachXO2 Family Data Sheet
Memory Usage Guide for MachXO2
Devices.
Architecture