LCMXO2-2000HC-4FTG256C Lattice, LCMXO2-2000HC-4FTG256C Datasheet - Page 37

• Manufacturer Part Number: LCMXO2-2000HC-4FTG256C
• Description: FPGA - Field Programmable Gate Array 2112 LUTs 207 IO 3.3V 4 Spd
• Manufacturer: Lattice

Specifications of LCMXO2-2000HC-4FTG256C

• Rohs: yes
• Number Of Gates: 2 K
• Embedded Block Ram - Ebr: 74 Kbit
• Number Of I/os: 207
• Maximum Operating Frequency: 269 MHz
• Operating Supply Voltage: 1.14 V to 3.465 V, 2.375 V to 3.465 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: ftBGA-256
• Distributed Ram: 16 Kbit
• Minimum Operating Temperature: 0 C
• Operating Supply Current: 4.8 mA
• Factory Pack Quantity: 90
• User Flash Memory - Ufm: 80 Kbit

Table 2-18. MachXO2 Power Saving Features Description
Bandgap
Power-On-Reset (POR)
On-Chip Oscillator
PLL
I/O Bank Controller
Dynamic Clock Enable for Primary
Clock Nets
Power Guard
For more details on the standby mode refer to TN1198,
Power On Reset
MachXO2 devices have power-on reset circuitry to monitor V
operation. At power-up, the POR circuitry monitors V
then triggers download from the on-chip configuration Flash memory after reaching the V
the Power-On-Reset Voltage table in the DC and Switching Characteristics section of this data sheet. For devices
without voltage regulators (ZE and HE devices), V
voltage regulators (HC devices), V
time taken for configuration and entry into user mode is specified as Flash Download Time (t
and Switching Characteristics section of this data sheet. Before and during configuration, the I/Os are held in tri-
state. I/Os are released to user functionality once the device has finished configuration. Note that for HC devices, a
separate POR circuit monitors external V
regulated power supply voltage level.
Once the device enters into user mode, the POR circuitry can optionally continue to monitor V
V
bandgap circuitry switched off to conserve power) device functionality cannot be guaranteed. In such a situation
the POR issues a reset and begins monitoring the V
are both specified in the Power-On-Reset Voltage table in the DC and Switching Characteristics section of this data
sheet.
Note that once a ZE or HE device enters user mode, users can switch off the bandgap to conserve power. When
the bandgap circuitry is switched off, the POR circuitry also shuts down. The device is designed such that a mini-
mal, low power POR circuit is still operational (this corresponds to the V
paragraph above). However this circuit is not as accurate as the one that operates when the bandgap is switched
on. The low power POR circuit emulates an SRAM cell and is biased to trip before the vast majority of SRAM cells
flip. If users are concerned about the V
or POR circuit.
CCINT
drops below V
Device Subsystem
PORDNBG
level (with the bandgap circuitry switched on) or below V
CCINT
The bandgap can be turned off in standby mode. When the Bandgap is turned off, ana-
log circuitry such as the POR, PLLs, on-chip oscillator, and referenced and differential 
I/O buffers are also turned off. Bandgap can only be turned off for 1.2V devices.
The POR can be turned off in standby mode. This monitors VCC levels. In the event of
unsafe V
off, limited power detector circuitry is still active. This option is only recommended for ap-
plications in which the power supply rails are reliable.
The on-chip oscillator has two power saving features. It may be switched off if it is not
needed in your design. It can also be turned off in Standby mode.
Similar to the on-chip oscillator, the PLL also has two power saving features. It can be
statically switched off if it is not needed in a design. It can also be turned off in Standby
mode. The PLL will wait until all output clocks from the PLL are driven low before power-
ing off.
Referenced and differential I/O buffers (used to implement standards such as HSTL,
SSTL and LVDS) consume more than ratioed single-ended I/Os such as LVCMOS and
LVTTL. The I/O bank controller allows the user to turn these I/Os off dynamically on a
per bank selection.
Each primary clock net can be dynamically disabled to save power.
Power Guard is a feature implemented in input buffers. This feature allows users to
switch off the input buffer when it is not needed. This feature can be used in both clock
and data paths. Its biggest impact is that in the standby mode it can be used to switch off
clock inputs that are distributed using general routing resources.
CC
is regulated from the V
CC
supply dropping below V
CC
voltage in addition to the POR circuit that monitors the internal post-
drops, this circuit reconfigures the device. When the POR circuitry is turned
CCINT
CCINT
CCINT
2-33
Power Estimation and Management for MachXO2
is the same as the V
and V
and V
CCINT
CC
CCIO
Feature Description
CC
supply voltage. From this voltage reference, the
CCIO0
and V
(min) they should not shut down the bandgap
voltage levels. V
(controls configuration) voltage levels. It
PORDNSRAM
CCIO
MachXO2 Family Data Sheet
CC
voltage levels during power-up and
supply voltage. For devices with
reset point described in the
PORDNBG
PORDNSRAM
PORUP
REFRESH
and V
level specified in
Architecture
CCINT
level (with the
PORDNSRAM
) in the DC
Devices.
levels. If