LCMXO2-2000HC-4FTG256C Lattice, LCMXO2-2000HC-4FTG256C Datasheet - Page 35

• Manufacturer Part Number: LCMXO2-2000HC-4FTG256C
• Description: FPGA - Field Programmable Gate Array 2112 LUTs 207 IO 3.3V 4 Spd
• Manufacturer: Lattice

Specifications of LCMXO2-2000HC-4FTG256C

• Rohs: yes
• Number Of Gates: 2 K
• Embedded Block Ram - Ebr: 74 Kbit
• Number Of I/os: 207
• Maximum Operating Frequency: 269 MHz
• Operating Supply Voltage: 1.14 V to 3.465 V, 2.375 V to 3.465 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: ftBGA-256
• Distributed Ram: 16 Kbit
• Minimum Operating Temperature: 0 C
• Operating Supply Current: 4.8 mA
• Factory Pack Quantity: 90
• User Flash Memory - Ufm: 80 Kbit

Figure 2-23. Timer/Counter Block Diagram
Table 2-17. Timer/Counter Signal Description
For more details on these embedded functions, please refer to TN1205,
Control Functions in MachXO2
tc_clki
tc_rstn
tc_ic
tc_int
tc_oc
• Supports the following modes of operation:
• Programmable clock input source
• Programmable input clock prescaler
• One static interrupt output to routing
• One wake-up interrupt to on-chip standby mode controller.
• Three independent interrupt sources: overflow, output compare match, and input capture
• Auto reload
• Time-stamping support on the input capture unit
• Waveform generation on the output
• Glitch-free PWM waveform generation with variable PWM period
• Internal WISHBONE bus access to the control and status registers
• Stand-alone mode with preloaded control registers and direct reset input
– Watchdog timer
– Clear timer on compare match
– Fast PWM
– Phase and Frequency Correct PWM
Port
Routing
I/O
Logic
O
O
Core
I
I
I
Timer/Counter input clock signal
Register tc_rstn_ena is preloaded by configuration to always keep this pin enabled
Input capture trigger event, applicable for non-pwm modes with WISHBONE interface. If
enabled, a rising edge of this signal will be detected and synchronized to capture tc_cnt value
into tc_icr for time-stamping.
Without WISHBONE – Can be used as overflow flag
With WISHBONE – Controlled by three IRQ registers
Timer counter output signal
Devices.
EFB
WISHBONE
Interface
EFB
Registers
Counter
Timer/
2-31
Description
Timer/Counter
Control
Logic
Using User Flash Memory and Hardened
MachXO2 Family Data Sheet
PWM
Architecture