LCMXO2-2000HC-4FTG256C Lattice, LCMXO2-2000HC-4FTG256C Datasheet - Page 38

• Manufacturer Part Number: LCMXO2-2000HC-4FTG256C
• Description: FPGA - Field Programmable Gate Array 2112 LUTs 207 IO 3.3V 4 Spd
• Manufacturer: Lattice

Specifications of LCMXO2-2000HC-4FTG256C

• Rohs: yes
• Number Of Gates: 2 K
• Embedded Block Ram - Ebr: 74 Kbit
• Number Of I/os: 207
• Maximum Operating Frequency: 269 MHz
• Operating Supply Voltage: 1.14 V to 3.465 V, 2.375 V to 3.465 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: ftBGA-256
• Distributed Ram: 16 Kbit
• Minimum Operating Temperature: 0 C
• Operating Supply Current: 4.8 mA
• Factory Pack Quantity: 90
• User Flash Memory - Ufm: 80 Kbit

Configuration and Testing
This section describes the configuration and testing features of the MachXO2 family.
IEEE 1149.1-Compliant Boundary Scan Testability
All MachXO2 devices have boundary scan cells that are accessed through an IEEE 1149.1 compliant test access
port (TAP). This allows functional testing of the circuit board, on which the device is mounted, through a serial scan
path that can access all critical logic nodes. Internal registers are linked internally, allowing test data to be shifted in
and loaded directly onto test nodes, or test data to be captured and shifted out for verification. The test access port
consists of dedicated I/Os: TDI, TDO, TCK and TMS. The test access port shares its power supply with V
Bank 0 and can operate with LVCMOS3.3, 2.5, 1.8, 1.5, and 1.2 standards.
For more details on boundary scan test, see AN8066,
TN1087,
Device Configuration
All MachXO2 devices contain two ports that can be used for device configuration. The Test Access Port (TAP),
which supports bit-wide configuration and the sysCONFIG port which supports serial configuration through I
SPI. The TAP supports both the IEEE Standard 1149.1 Boundary Scan specification and the IEEE Standard 1532
In-System Configuration specification. There are various ways to configure a MachXO2 device:
1. Internal Flash Download
2. JTAG
3. Standard Serial Peripheral Interface (Master SPI mode) – interface to boot PROM memory
4. System microprocessor to drive a serial slave SPI port (SSPI mode)
5. Standard I
Upon power-up, the configuration SRAM is ready to be configured using the selected sysCONFIG port. Once a
configuration port is selected, it will remain active throughout that configuration cycle. The IEEE 1149.1 port can be
activated any time after power-up by sending the appropriate command through the TAP port. Optionally the de-
vice can run a CRC check upon entering the user mode. This will ensure that the device was configured correctly.
The sysCONFIG port has 10 dual-function pins which can be used as general purpose I/Os if they are not required
for configuration. See TN1204,
about using the dual-use pins as general purpose I/Os.
Lattice design software uses proprietary compression technology to compress bit-streams for use in MachXO2
devices. Use of this technology allows Lattice to provide a lower cost solution. In the unlikely event that this technol-
ogy is unable to compress bitstreams to fit into the amount of on-chip Flash memory, there are a variety of tech-
niques that can be utilized to allow the bitstream to fit in the on-chip Flash memory. For more details, refer to
TN1204,
The Test Access Port (TAP) has five dual purpose pins (TDI, TDO, TMS and TCK). These pins are dual function
pins - TDI, TDO, TMS and TCK can be used as general purpose I/O if desired. For more details, refer to TN1204,
MachXO2 Programming and Configuration Usage
TransFR (Transparent Field Reconfiguration)
TransFR is a unique Lattice technology that allows users to update their logic in the field without interrupting sys-
tem operation using a simple push-button solution. For more details refer to TN1087,
tion During Configuration Using TransFR Technology
Security and One-Time Programmable Mode (OTP)
Minimizing System Interruption During Configuration Using TransFR
MachXO2 Programming and Configuration Usage
2
C Interface to system microprocessor
MachXO2 Programming and Configuration Usage Guide
Guide.
for details.
Boundary Scan Testability with Lattice sysIO Capability
2-34
Guide.
MachXO2 Family Data Sheet
Technology.
Minimizing System Interrup-
for more information
Architecture
2
CCIO
C or
and