LCMXO2-2000HC-4FTG256C Lattice, LCMXO2-2000HC-4FTG256C Datasheet - Page 104

• Manufacturer Part Number: LCMXO2-2000HC-4FTG256C
• Description: FPGA - Field Programmable Gate Array 2112 LUTs 207 IO 3.3V 4 Spd
• Manufacturer: Lattice

Specifications of LCMXO2-2000HC-4FTG256C

• Rohs: yes
• Number Of Gates: 2 K
• Embedded Block Ram - Ebr: 74 Kbit
• Number Of I/os: 207
• Maximum Operating Frequency: 269 MHz
• Operating Supply Voltage: 1.14 V to 3.465 V, 2.375 V to 3.465 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: ftBGA-256
• Distributed Ram: 16 Kbit
• Minimum Operating Temperature: 0 C
• Operating Supply Current: 4.8 mA
• Factory Pack Quantity: 90
• User Flash Memory - Ufm: 80 Kbit

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January 2013
November 2010
January 2011
April 2011
May 2011
Date
Version
01.0
01.1
01.2
01.3
Ordering Information
Pinout Information
Pinout Information
DC and Switching
DC and Switching
DC and Switching
Characteristics
Characteristics
Characteristics
Architecture
Introduction
Section
Multiple
All
—
—
Initial release.
Included ultra-high I/O devices.
Recommended Operating Conditions table – Added footnote 3.
DC Electrical Characteristics table – Updated data for I
ical values updated.
Generic DDRX2 Outputs with Clock and Data Aligned at Pin
(GDDRX2_TX.ECLK.Aligned) Using PCLK Pin for Clock Input tables –
Updated data for T
Generic DDRX4 Outputs with Clock and Data Aligned at Pin
(GDDRX4_TX.ECLK.Aligned) Using PCLK Pin for Clock Input tables –
Updated data for T
Power-On-Reset Voltage Levels table - clarified note 3.
Clarified VCCIO related recommended operating conditions specifica-
tions.
Added power supply ramp rate requirements.
Added Power Supply Ramp Rates table.
Updated Programming/Erase Specifications table.
Removed references to V
Included number of 7:1 and 8:1 gearboxes (input and output) in the pin
information summary tables.
Removed references to V
Data sheet status changed from Advance to Preliminary.
Updated MachXO2 Family Selection Guide table.
Updated Supported Input Standards table.
Updated sysMEM Memory Primitives diagram.
Added differential SSTL and HSTL IO standards.
Updates following parameters: POR voltage levels, DC electrical char-
acteristics, static supply current for ZE/HE/HC devices, static power
consumption contribution of different components – ZE devices, pro-
gramming and erase Flash supply current.
Added VREF specifications to sysIO recommended operating condi-
tions.
Updating timing information based on characterization.
Added differential SSTL and HSTL IO standards.
Added Ordering Part Numbers for R1 devices, and devices in WLCSP
packages.
Added R1 device specifications.
Replaced “SED” with “SRAM CRC Error Detection” throughout the doc-
ument.
Added footnote 1 to Program Erase Specifications table.
Updated Pin Information Summary tables.
Signal name SO/SISPISO changed to SO/SPISO in the Signal Descrip-
tions table.
MachXO2 Family Data Sheet
7-1
DIA
DIA
and T
and T
CCP.
CCP.
Change Summary
DIB.
DIB.
Revision History
DS1035 Revision History
Data Sheet DS1035
IL
, I
IH
. V
HYST
typ-