LCMXO2-2000HC-4FTG256C Lattice, LCMXO2-2000HC-4FTG256C Datasheet - Page 39

• Manufacturer Part Number: LCMXO2-2000HC-4FTG256C
• Description: FPGA - Field Programmable Gate Array 2112 LUTs 207 IO 3.3V 4 Spd
• Manufacturer: Lattice

Specifications of LCMXO2-2000HC-4FTG256C

• Rohs: yes
• Number Of Gates: 2 K
• Embedded Block Ram - Ebr: 74 Kbit
• Number Of I/os: 207
• Maximum Operating Frequency: 269 MHz
• Operating Supply Voltage: 1.14 V to 3.465 V, 2.375 V to 3.465 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: ftBGA-256
• Distributed Ram: 16 Kbit
• Minimum Operating Temperature: 0 C
• Operating Supply Current: 4.8 mA
• Factory Pack Quantity: 90
• User Flash Memory - Ufm: 80 Kbit

Architecture
MachXO2 Family Data Sheet
For applications where security is important, the lack of an external bitstream provides a solution that is inherently
more secure than SRAM-based FPGAs. This is further enhanced by device locking. MachXO2 devices contain
security bits that, when set, prevent the readback of the SRAM configuration and non-volatile Flash memory
spaces. The device can be in one of two modes:
1. Unlocked – Readback of the SRAM configuration and non-volatile Flash memory spaces is allowed.
2. Permanently Locked – The device is permanently locked.
Once set, the only way to clear the security bits is to erase the device. To further complement the security of the
device, a One Time Programmable (OTP) mode is available. Once the device is set in this mode it is not possible to
erase or re-program the Flash and SRAM OTP portions of the device. For more details, refer to TN1204,
MachXO2
Programming and Configuration Usage
Guide.
Dual Boot
MachXO2 devices can optionally boot from two patterns, a primary bitstream and a golden bitstream. If the primary
bitstream is found to be corrupt while being downloaded into the SRAM, the device shall then automatically re-boot
from the golden bitstream. Note that the primary bitstream must reside in the on-chip Flash. The golden image
MUST reside in an external SPI Flash. For more details, refer to TN1204,
MachXO2 Programming and Configura-
tion Usage
Guide.
Soft Error Detection
The SED feature is a CRC check of the SRAM cells after the device is configured. This check ensures that the
SRAM cells were configured successfully. This feature is enabled by a configuration bit option. The Soft Error
Detection can also be initiated in user mode via an input to the fabric. The clock for the Soft Error Detection circuit
is generated using a dedicated divider. The undivided clock from the on-chip oscillator is the input to this divider.
For low power applications users can switch off the Soft Error Detection circuit. For more details, refer to TN1206,
MachXO2 Soft Error Detection Usage
Guide.
TraceID
Each MachXO2 device contains a unique (per device), TraceID that can be used for tracking purposes or for IP
security applications. The TraceID is 64 bits long. Eight out of 64 bits are user-programmable, the remaining 56 bits
are factory-programmed. The TraceID is accessible through the EFB WISHBONE interface and can also be
2
accessed through the SPI, I
C, or JTAG interfaces.
Density Shifting
The MachXO2 family has been designed to enable density migration within the same package. Furthermore, the
architecture ensures a high success rate when performing design migration from lower density devices to higher
density devices. In many cases, it is also possible to shift a lower utilization design targeted for a high-density
device to a lower density device. However, the exact details of the final resource utilization will impact the likely suc-
cess in each case. For more details refer to the
MachXO2 migration
files.
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