LCMXO2-2000HC-4FTG256C Lattice, LCMXO2-2000HC-4FTG256C Datasheet - Page 7

• Manufacturer Part Number: LCMXO2-2000HC-4FTG256C
• Description: FPGA - Field Programmable Gate Array 2112 LUTs 207 IO 3.3V 4 Spd
• Manufacturer: Lattice

Specifications of LCMXO2-2000HC-4FTG256C

• Rohs: yes
• Number Of Gates: 2 K
• Embedded Block Ram - Ebr: 74 Kbit
• Number Of I/os: 207
• Maximum Operating Frequency: 269 MHz
• Operating Supply Voltage: 1.14 V to 3.465 V, 2.375 V to 3.465 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: ftBGA-256
• Distributed Ram: 16 Kbit
• Minimum Operating Temperature: 0 C
• Operating Supply Current: 4.8 mA
• Factory Pack Quantity: 90
• User Flash Memory - Ufm: 80 Kbit

Slices
Slices 0-3 contain two LUT4s feeding two registers. Slices 0-2 can be configured as distributed memory. Table 2-1
shows the capability of the slices in PFU blocks along with the operation modes they enable. In addition, each PFU
contains logic that allows the LUTs to be combined to perform functions such as LUT5, LUT6, LUT7 and LUT8.
The control logic performs set/reset functions (programmable as synchronous/ asynchronous), clock select, chip-
select and wider RAM/ROM functions.
Table 2-1. Resources and Modes Available per Slice
Figure 2-4 shows an overview of the internal logic of the slice. The registers in the slice can be configured for posi-
tive/negative and edge triggered or level sensitive clocks. All slices have 15 inputs from routing and one from the
carry-chain (from the adjacent slice or PFU). There are seven outputs: six for routing and one to carry-chain (to the
adjacent PFU). Table 2-2 lists the signals associated with Slices 0-3.
Figure 2-4. Slice Diagram
Routing
From
Slice 0
Slice 1
Slice 2
Slice 3
Slice
FXB
FXA
CLK
LSR
M1
M0
CE
C1
D1
C0
D0
A1
B1
A0
B0
For Slices 0 and 1, memory control signals are generated from Slice 2 as follows:
• WCK is CLK
• WRE is from LSR
• DI[3:2] for Slice 1 and DI[1:0] for Slice 0 data from Slice 2
• WAD [A:D] is a 4-bit address from slice 2 LUT input
2 LUT4s and 2 Registers
2 LUT4s and 2 Registers
2 LUT4s and 2 Registers
2 LUT4s and 2 Registers
Memory &
Control
Resources
Signals
FCO To Different Slice/PFU
FCI From
Slice/PFU
Different
LUT4 &
LUT4 &
Carry
Carry
CO
CO
CI
CI
2-3
PFU Block
F/SUM
F/SUM
Logic, Ripple, RAM, ROM
Logic, Ripple, RAM, ROM
Logic, Ripple, RAM, ROM
LUT5
Logic, Ripple, ROM
Mux
Modes
MachXO2 Family Data Sheet
D
D
Flip-flop/
Flip-flop/
Latch
Latch
Slice
Routing
OFX1
F1
Q1
To
OFX0
F0
Q0
Architecture