LCMXO2-2000HC-4FTG256C Lattice, LCMXO2-2000HC-4FTG256C Datasheet - Page 65

• Manufacturer Part Number: LCMXO2-2000HC-4FTG256C
• Description: FPGA - Field Programmable Gate Array 2112 LUTs 207 IO 3.3V 4 Spd
• Manufacturer: Lattice

Specifications of LCMXO2-2000HC-4FTG256C

• Rohs: yes
• Number Of Gates: 2 K
• Embedded Block Ram - Ebr: 74 Kbit
• Number Of I/os: 207
• Maximum Operating Frequency: 269 MHz
• Operating Supply Voltage: 1.14 V to 3.465 V, 2.375 V to 3.465 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: ftBGA-256
• Distributed Ram: 16 Kbit
• Minimum Operating Temperature: 0 C
• Operating Supply Current: 4.8 mA
• Factory Pack Quantity: 90
• User Flash Memory - Ufm: 80 Kbit

Generic DDR4 Inputs with Clock and Data Centered at Pin Using PCLK Pin for Clock Input – GDDRX4_RX.ECLK.Centered
t
t
f
f
f
7:1 LVDS Inputs – GDDR71_RX.ECLK.7.1
t
t
f
f
f
Generic DDR Outputs with Clock and Data Aligned at Pin Using PCLK Pin for Clock Input – GDDRX1_TX.SCLK.Aligned
t
t
f
f
Generic DDR Outputs with Clock and Data Centered at Pin Using PCLK Pin for Clock Input – GDDRX1_TX.SCLK.Centered
t
t
f
f
Generic DDRX2 Outputs with Clock and Data Aligned at Pin Using PCLK Pin for Clock Input – GDDRX2_TX.ECLK.Aligned
t
t
f
f
f
SU
HO
DATA
DDRX4
SCLK
DVA
DVE
DATA
DDR71
CLKIN
DIA
DIB
DATA
DDRX1
DVB
DVA
DATA
DDRX1
DIA
DIB
DATA
DDRX2
SCLK
Parameter
Input Data Setup Before ECLK
Input Data Hold After ECLK
DDRX4 Serial Input Data
Speed
DDRX4 ECLK Frequency
SCLK Frequency
Input Data Valid After ECLK
Input Data Hold After ECLK
DDR71 Serial Input Data
Speed
DDR71 ECLK Frequency
7:1 Input Clock Frequency
(SCLK) (minimum limited by
PLL)
Output Data Invalid After CLK
Output
Output Data Invalid Before
CLK Output
DDRX1 Output Data Speed
DDRX1 SCLK frequency
Output Data Valid Before CLK
Output
Output Data Valid After CLK
Output
DDRX1 Output Data Speed
DDRX1 SCLK Frequency
(minimum limited by PLL)
Output Data Invalid After CLK
Output
Output Data Invalid Before
CLK Output
DDRX2 Serial Output Data
Speed
DDRX2 ECLK frequency
SCLK Frequency
Description
9
MachXO2-640U,
MachXO2-1200/U
and larger devices,
bottom side only
MachXO2-640U,
MachXO2-1200/U
and larger devices,
bottom side only
All MachXO2
devices, all sides
All MachXO2
devices, all sides
MachXO2-640U,
MachXO2-1200/U
and larger devices,
top side only
Device
3-26
0.434
0.385
0.662
2.720
2.720
Min.
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
-3
DC and Switching Characteristics
0.307
0.850
0.850
0.270
0.270
Max.
420
210
420
210
140
140
280
140
—
—
53
—
60
70
—
—
70
70
MachXO2 Family Data Sheet
0.535
0.395
0.650
3.380
3.380
Min.
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
-2
0.316
0.910
0.910
0.300
0.300
Max.
352
176
352
176
116
116
234
117
44
50
58
58
59
—
—
—
—
—
0.630
0.463
0.649
4.140
4.140
Min.
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
-1
0.326
0.970
0.970
0.330
0.330
Max.
292
146
292
146
194
37
42
98
49
98
49
97
49
—
—
—
—
—
Units
Mbps
Mbps
Mbps
Mbps
Mbps
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
UI
UI
9
9
9
9