LCMXO2-2000HC-4FTG256C Lattice, LCMXO2-2000HC-4FTG256C Datasheet - Page 6

• Manufacturer Part Number: LCMXO2-2000HC-4FTG256C
• Description: FPGA - Field Programmable Gate Array 2112 LUTs 207 IO 3.3V 4 Spd
• Manufacturer: Lattice

Specifications of LCMXO2-2000HC-4FTG256C

• Rohs: yes
• Number Of Gates: 2 K
• Embedded Block Ram - Ebr: 74 Kbit
• Number Of I/os: 207
• Maximum Operating Frequency: 269 MHz
• Operating Supply Voltage: 1.14 V to 3.465 V, 2.375 V to 3.465 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: ftBGA-256
• Distributed Ram: 16 Kbit
• Minimum Operating Temperature: 0 C
• Operating Supply Current: 4.8 mA
• Factory Pack Quantity: 90
• User Flash Memory - Ufm: 80 Kbit

The logic blocks, Programmable Functional Unit (PFU) and sysMEM EBR blocks, are arranged in a two-dimen-
sional grid with rows and columns. Each row has either the logic blocks or the EBR blocks. The PIO cells are
located at the periphery of the device, arranged in banks. The PFU contains the building blocks for logic, arithmetic,
RAM, ROM, and register functions. The PIOs utilize a flexible I/O buffer referred to as a sysIO buffer that supports
operation with a variety of interface standards. The blocks are connected with many vertical and horizontal routing
channel resources. The place and route software tool automatically allocates these routing resources.
In the MachXO2 family, the number of sysIO banks varies by device. There are different types of I/O buffers on the
different banks. Refer to the details in later sections of this document. The sysMEM EBRs are large, dedicated fast
memory blocks; these blocks are found in MachXO2-640/U and larger devices. These blocks can be configured as
RAM, ROM or FIFO. FIFO support includes dedicated FIFO pointer and flag “hard” control logic to minimize LUT
usage.
The MachXO2 architecture also provides up to two sysCLOCK Phase Locked Loop (PLL) blocks on MachXO2-
640U, MachXO2-1200/U and larger devices. These blocks are located at the ends of the on-chip Flash block. The
PLLs have multiply, divide, and phase shifting capabilities that are used to manage the frequency and phase rela-
tionships of the clocks.
MachXO2 devices provide commonly used hardened functions such as SPI controller, I
counter. MachXO2-640/U and higher density devices also provide User Flash Memory (UFM). These hardened
functions and the UFM interface to the core logic and routing through a WISHBONE interface. The UFM can also
be accessed through the SPI, I
Every device in the family has a JTAG port that supports programming and configuration of the device as well as
access to the user logic. The MachXO2 devices are available for operation from 3.3V, 2.5V and 1.2V power sup-
plies, providing easy integration into the overall system.
PFU Blocks
The core of the MachXO2 device consists of PFU blocks, which can be programmed to perform logic, arithmetic,
distributed RAM and distributed ROM functions. Each PFU block consists of four interconnected slices numbered 0
to 3 as shown in Figure 2-3. Each slice contains two LUTs and two registers. There are 53 inputs and 25 outputs
associated with each PFU block.
Figure 2-3. PFU Block Diagram
FCIN
Latch
FF/
CARRY
LUT4 &
D
Slice 0
Latch
FF/
CARRY
LUT4 &
D
2
C and JTAG ports.
Latch
FF/
CARRY
LUT4 &
D
Slice 1
Latch
FF/
CARRY
LUT4 &
D
Routin g
Routin g
From
2-2
To
Latch
FF/
CARRY
LUT4 &
D
Slice 2
Latch
FF/
CARRY
LUT4 &
D
MachXO2 Family Data Sheet
Latch
FF/
CARRY
LUT4 &
D
Slice 3
2
C controller and timer/
Latch
FF/
LUT4 &
CARRY
D
Architecture
FCO