LCMXO2-2000HC-4FTG256C Lattice, LCMXO2-2000HC-4FTG256C Datasheet - Page 34

• Manufacturer Part Number: LCMXO2-2000HC-4FTG256C
• Description: FPGA - Field Programmable Gate Array 2112 LUTs 207 IO 3.3V 4 Spd
• Manufacturer: Lattice

Specifications of LCMXO2-2000HC-4FTG256C

• Rohs: yes
• Number Of Gates: 2 K
• Embedded Block Ram - Ebr: 74 Kbit
• Number Of I/os: 207
• Maximum Operating Frequency: 269 MHz
• Operating Supply Voltage: 1.14 V to 3.465 V, 2.375 V to 3.465 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: ftBGA-256
• Distributed Ram: 16 Kbit
• Minimum Operating Temperature: 0 C
• Operating Supply Current: 4.8 mA
• Factory Pack Quantity: 90
• User Flash Memory - Ufm: 80 Kbit

There are some limitations on the use of the hardened user SPI. These are defined in the following technical notes:
Figure 2-22. SPI Core Block Diagram
Table 2-16 describes the signals interfacing with the SPI cores.
Table 2-16. SPI Core Signal Description
Hardened Timer/Counter
MachXO2 devices provide a hard Timer/Counter IP core. This Timer/Counter is a general purpose, bi-directional,
16-bit timer/counter module with independent output compare units and PWM support. The Timer/Counter sup-
ports the following functions:
spi_csn[0]
spi_csn[1..7]
spi_scsn
spi_irq
spi_clk
spi_miso
spi_mosi
ufm_sn
cfg_stdby
cfg_wake
Signal Name
• TN1087,
• TN1205,
Minimizing System Interruption During Configuration Using TransFR Technology
Using User Flash Memory and Hardened Control Functions in MachXO2 Devices
I/O
I/O
I/O
I/O
O
O
O
O
O
I
I
Routing
Logic/
Core
Master/Slave
Master/Slave
Master/Slave
Master/Slave
Master/Slave
Master/Slave
Master/Slave
Master
Master
Slave
Slave
EFB
WISHBONE
Interface
EFB
SPI master chip-select output
Additional SPI chip-select outputs (total up to eight slaves)
SPI slave chip-select input
Interrupt request
SPI clock. Output in master mode. Input in slave mode.
SPI data. Input in master mode. Output in slave mode.
SPI data. Output in master mode. Input in slave mode.
Configuration Slave Chip Select (active low), dedicated for selecting the
User Flash Memory (UFM).
Stand-by signal – To be connected only to the power module of the MachXO2
device. The signal is enabled only if the “Wakeup Enable” feature has been
set within the EFB GUI, SPI Tab.
Wake-up signal – To be connected only to the power module of the MachXO2
device. The signal is enabled only if the “Wakeup Enable” feature has been
set within the EFB GUI, SPI Tab.
2-30
Registers
SPI
Configuration
SPI Function
Logic
Control
Logic
Description
MachXO2 Family Data Sheet
MCSN
MISO
MOSI
SCSN
SCK
(Appendix B)
Architecture