LCMXO2-2000HC-4FTG256C Lattice, LCMXO2-2000HC-4FTG256C Datasheet - Page 36

• Manufacturer Part Number: LCMXO2-2000HC-4FTG256C
• Description: FPGA - Field Programmable Gate Array 2112 LUTs 207 IO 3.3V 4 Spd
• Manufacturer: Lattice

Specifications of LCMXO2-2000HC-4FTG256C

• Rohs: yes
• Number Of Gates: 2 K
• Embedded Block Ram - Ebr: 74 Kbit
• Number Of I/os: 207
• Maximum Operating Frequency: 269 MHz
• Operating Supply Voltage: 1.14 V to 3.465 V, 2.375 V to 3.465 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: ftBGA-256
• Distributed Ram: 16 Kbit
• Minimum Operating Temperature: 0 C
• Operating Supply Current: 4.8 mA
• Factory Pack Quantity: 90
• User Flash Memory - Ufm: 80 Kbit

User Flash Memory (UFM)
MachXO2-640/U and higher density devices provide a User Flash Memory block, which can be used for a variety of
applications including storing a portion of the configuration image, initializing EBRs, to store PROM data or, as a
general purpose user Flash memory. The UFM block connects to the device core through the embedded function
block WISHBONE interface. Users can also access the UFM block through the JTAG, I
device. The UFM block offers the following features:
For more information on the UFM, please refer to TN1205,
tions in MachXO2
Standby Mode and Power Saving Options
MachXO2 devices are available in three options for maximum flexibility: ZE, HC and HE devices. The ZE devices
have ultra low static and dynamic power consumption. These devices use a 1.2V core voltage that further reduces
power consumption. The HC and HE devices are designed to provide high performance. The HC devices have a
built-in voltage regulator to allow for 2.5V V
MachXO2 devices have been designed with features that allow users to meet the static and dynamic power
requirements of their applications by controlling various device subsystems such as the bandgap, power-on-reset
circuitry, I/O bank controllers, power guard, on-chip oscillator, PLLs, etc. In order to maximize power savings,
MachXO2 devices support an ultra low power Stand-by mode. While most of these features are available in all
three device types, these features are mainly intended for use with MachXO2 ZE devices to manage power con-
sumption.
In the stand-by mode the MachXO2 devices are powered on and configured. Internal logic, I/Os and memories are
switched on and remain operational, as the user logic waits for an external input. The device enters this mode
when the standby input of the standby controller is toggled or when an appropriate I
by an external master. Various subsystems in the device such as the band gap, power-on-reset circuitry etc can be
configured such that they are automatically turned “off” or go into a low power consumption state to save power
when the device enters this state.
• Non-volatile storage up to 256Kbits
• 100K write cycles
• Write access is performed page-wise; each page has 128 bits (16 bytes)
• Auto-increment addressing
• WISHBONE interface
Devices.
CC
and 3.3V V
2-32
CC
Using User Flash Memory and Hardened Control Func-
while the HE devices operate at 1.2V V
MachXO2 Family Data Sheet
2
C or JTAG instruction is issued
2
C and SPI interfaces of the
Architecture
CC
.