LCMXO2-2000HC-4FTG256C Lattice, LCMXO2-2000HC-4FTG256C Datasheet - Page 19

• Manufacturer Part Number: LCMXO2-2000HC-4FTG256C
• Description: FPGA - Field Programmable Gate Array 2112 LUTs 207 IO 3.3V 4 Spd
• Manufacturer: Lattice

Specifications of LCMXO2-2000HC-4FTG256C

• Rohs: yes
• Number Of Gates: 2 K
• Embedded Block Ram - Ebr: 74 Kbit
• Number Of I/os: 207
• Maximum Operating Frequency: 269 MHz
• Operating Supply Voltage: 1.14 V to 3.465 V, 2.375 V to 3.465 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: ftBGA-256
• Distributed Ram: 16 Kbit
• Minimum Operating Temperature: 0 C
• Operating Supply Current: 4.8 mA
• Factory Pack Quantity: 90
• User Flash Memory - Ufm: 80 Kbit

PIO
The PIO contains three blocks: an input register block, output register block and tri-state register block. These
blocks contain registers for operating in a variety of modes along with the necessary clock and selection logic.
Table 2-8. PIO Signal List
Input Register Block
The input register blocks for the PIOs on all edges contain delay elements and registers that can be used to condi-
tion high-speed interface signals before they are passed to the device core. In addition to this functionality, the input
register blocks for the PIOs on the right edge include built-in logic to interface to DDR memory.
Figure 2-12 shows the input register block for the PIOs located on the left, top and bottom edges. Figure 2-13
shows the input register block for the PIOs on the right edge.
Left, Top, Bottom Edges
Input signals are fed from the sysIO buffer to the input register block (as signal D). If desired, the input signal can
bypass the register and delay elements and be used directly as a combinatorial signal (INDD), and a clock (INCK).
If an input delay is desired, users can select a fixed delay. I/Os on the bottom edge also have a dynamic delay,
DEL[4:0]. The delay, if selected, reduces input register hold time requirements when using a global clock. The input
block allows two modes of operation. In single data rate (SDR) the data is registered with the system clock (SCLK)
by one of the registers in the single data rate sync register block. In Generic DDR mode, two registers are used to
sample the data on the positive and negative edges of the system clock (SCLK) signal, creating two data streams.
CE
D
INDD
INCK
Q0
Q1
D0
D1
TD
Q
TQ
DQSR90
DQSW90
DDRCLKPOL
SCLK
RST
1. Available in PIO on right edge only.
Pin Name
1
1
1
I/O Type
Output
Output
Output
Output
Output
Output
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Clock Enable
Pin input from sysIO buffer.
Register bypassed input.
Clock input
DDR positive edge input
Registered input/DDR negative edge input
Output signal from the core (SDR and DDR)
Output signal from the core (DDR)
Tri-state signal from the core
Data output signals to sysIO Buffer
Tri-state output signals to sysIO Buffer
DQS shift 90-degree read clock
DQS shift 90-degree write clock
DDR input register polarity control signal from DQS
System clock for input and output/tri-state blocks.
Local set reset signal
2-15
Description
MachXO2 Family Data Sheet
Architecture