LCMXO2-2000HC-4FTG256C Lattice, LCMXO2-2000HC-4FTG256C Datasheet - Page 2

• Manufacturer Part Number: LCMXO2-2000HC-4FTG256C
• Description: FPGA - Field Programmable Gate Array 2112 LUTs 207 IO 3.3V 4 Spd
• Manufacturer: Lattice

Specifications of LCMXO2-2000HC-4FTG256C

• Rohs: yes
• Number Of Gates: 2 K
• Embedded Block Ram - Ebr: 74 Kbit
• Number Of I/os: 207
• Maximum Operating Frequency: 269 MHz
• Operating Supply Voltage: 1.14 V to 3.465 V, 2.375 V to 3.465 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: ftBGA-256
• Distributed Ram: 16 Kbit
• Minimum Operating Temperature: 0 C
• Operating Supply Current: 4.8 mA
• Factory Pack Quantity: 90
• User Flash Memory - Ufm: 80 Kbit

January 2013
Features
 Flexible Logic Architecture
 Ultra Low Power Devices
 Embedded and Distributed Memory
 On-Chip User Flash Memory
 Pre-Engineered Source Synchronous I/O
 High Performance, Flexible I/O Buffer
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or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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• Six devices with 256 to 6864 LUT4s and 
• Advanced 65 nm low power process
• As low as 19 µW standby power
• Programmable low swing differential I/Os
• Stand-by mode and other power saving options
• Up to 240 Kbits sysMEM™ Embedded Block
• Up to 54 Kbits Distributed RAM
• Dedicated FIFO control logic
• Up to 256 Kbits of User Flash Memory
• 100,000 write cycles
• Accessible through WISHBONE, SPI, I
• Can be used as soft processor PROM or as
• DDR registers in I/O cells
• Dedicated gearing logic
• 7:1 Gearing for Display I/Os
• Generic DDR, DDRX2, DDRX4
• Dedicated DDR/DDR2/LPDDR memory with
• Programmable sysIO™ buffer supports wide
• I/Os support hot socketing
• On-chip differential termination
• Programmable pull-up or pull-down mode
19 to 335 I/Os
RAM
JTAG interfaces
Flash memory
DQS support
range of interfaces:
– LVCMOS 3.3/2.5/1.8/1.5/1.2
– LVTTL
– PCI
– LVDS, Bus-LVDS, MLVDS, RSDS, LVPECL
– SSTL 25/18
– HSTL 18
– Schmitt trigger inputs, up to 0.5V hysteresis
2
C and
MachXO2 Family Data Sheet
1-1
 Flexible On-Chip Clocking
 Non-volatile, Infinitely Reconfigurable
 TransFR™ Reconfiguration
 Enhanced System Level Support
 Broad Range of Package Options
• Eight primary clocks
• Up to two edge clocks for high-speed I/O 
• Up to two analog PLLs per device with 
• Instant-on – powers up in microseconds
• Single-chip, secure solution
• Programmable through JTAG, SPI or I
• Supports background programming of non-vola-
• Optional dual boot with external SPI memory
• In-field logic update while system operates
• On-chip hardened functions: SPI, I
• On-chip oscillator with 5.5% accuracy
• Unique TraceID for system tracking
• One Time Programmable (OTP) mode
• Single power supply with extended operating
• IEEE Standard 1149.1 boundary scan
• IEEE 1532 compliant in-system programming
• TQFP, WLCSP, ucBGA, csBGA, caBGA, ftBGA,
• Small footprint package options
• Density migration supported
• Advanced halogen-free packaging
interfaces (top and bottom sides only)
fractional-n frequency synthesis
tile memory
counter
range
fpBGA, QFN package options
– Wide input frequency range (10 MHz to 
– As small as 2.5x2.5mm
400 MHz)
Introduction
DS1035
Data Sheet DS1035
Introduction_01.6
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C, timer/
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