LCMXO2-2000HC-4FTG256C Lattice, LCMXO2-2000HC-4FTG256C Datasheet - Page 103

• Manufacturer Part Number: LCMXO2-2000HC-4FTG256C
• Description: FPGA - Field Programmable Gate Array 2112 LUTs 207 IO 3.3V 4 Spd
• Manufacturer: Lattice

Specifications of LCMXO2-2000HC-4FTG256C

• Rohs: yes
• Number Of Gates: 2 K
• Embedded Block Ram - Ebr: 74 Kbit
• Number Of I/os: 207
• Maximum Operating Frequency: 269 MHz
• Operating Supply Voltage: 1.14 V to 3.465 V, 2.375 V to 3.465 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: ftBGA-256
• Distributed Ram: 16 Kbit
• Minimum Operating Temperature: 0 C
• Operating Supply Current: 4.8 mA
• Factory Pack Quantity: 90
• User Flash Memory - Ufm: 80 Kbit

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April 2012
For Further Information
A variety of technical notes for the MachXO2 family are available on the Lattice web site.
• TN1198,
• TN1199,
• TN1201,
• TN1202,
• TN1203,
• TN1204,
• TN1205,
• TN1206,
• TN1207,
• TN1074,
• TN1087,
• AN8086,
• AN8066,
•
•
•
For further information on interface standards, refer to the following web sites:
• JEDEC Standards (LVTTL, LVCMOS, LVDS, DDR, DDR2, LPDDR):
• PCI:
MachXO2 Device Pinout Files
Thermal Management
Lattice design tools
www.pcisig.com
Power Estimation and Management for MachXO2 Devices
MachXO2 sysCLOCK PLL Design and Usage Guide
Memory Usage Guide for MachXO2 Devices
MachXO2 sysIO Usage Guide
Implementing High-Speed Interfaces with MachXO2 Devices
MachXO2 Programming and Configuration Usage Guide
Using User Flash Memory and Hardened Control Functions in MachXO2 Devices
MachXO2 SRAM CRC Error Detection Usage Guide
Using TraceID in MachXO2 Devices
PCB Layout Recommendations for BGA Packages
Minimizing System Interruption During Configuration Using TransFR Technology
Designing for Migration from MachXO2-1200-R1 to Standard (non-R1) Devices
Boundary Scan Testability with Lattice sysIO Capability
document
MachXO2 Family Data Sheet
6-1
Supplemental Information
www.jedec.org
DS1035
Data Sheet DS1035
Further Info_01.3