MC9S12C128MFAE Freescale Semiconductor, MC9S12C128MFAE Datasheet - Page 102
![IC MCU 128K FLASH 25MHZ 48-LQFP](/photos/12/20/122066/mc9s12c128mfae_sml.jpg)
MC9S12C128MFAE
Manufacturer Part Number
MC9S12C128MFAE
Description
IC MCU 128K FLASH 25MHZ 48-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Specifications of MC9S12C128MFAE
Core Processor
HCS12
Core Size
16-Bit
Speed
25MHz
Connectivity
CAN, EBI/EMI, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
31
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.35 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
48-LQFP
Processor Series
S12C
Core
HCS12
Data Bus Width
16 bit
Data Ram Size
4 KB
Interface Type
CAN/SCI/SPI
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
31
Number Of Timers
8
Operating Supply Voltage
3.3 V to 5.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
M68EVB912C32EE
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Package
48LQFP
Family Name
HCS12
Maximum Speed
25 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC9S12C128MFAE
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Chapter 2 Port Integration Module (PIM9C32) Block Description
2.3.2.6.3
Read: Anytime.
Write: Anytime.
2.3.2.6.4
Read: Anytime.
Write: Anytime.
102
Module Base + 0x0032
Module Base + 0x0033
DDRAD[7:0]
RDRAD[7:0]
Reset
Reset
Field
Field
7–0
7–0
W
W
R
R
DDRAD7
RDRAD7
Data Direction Port AD — This register configures port pins AD[7:0] as either input or output.
0 Associated pin is configured as input.
1 Associated pin is configured as output.
Note: Due to internal synchronization circuits, it can take up to 2 bus cycles until the correct value is read on
Reduced Drive Port AD — This register configures the drive strength of each port AD output pin as either full
or reduced. If the port is used as input this bit is ignored.
0 Full drive strength at output.
1 Associated pin drives at about 1/3 of the full drive strength.
0
0
7
7
Port AD Data Direction Register (DDRAD)
Port AD Reduced Drive Register (RDRAD)
PTAD or PTIAD registers, when changing the DDRAD register.
DDRAD6
RDRAD6
Figure 2-43. Port AD Reduced Drive Register (RDRAD)
0
Figure 2-42. Port AD Data Direction Register (DDRAD)
0
6
6
Table 2-34. DDRAD Field Descriptions
Table 2-35. RDRAD Field Descriptions
DDRAD5
RDRAD5
MC9S12C-Family / MC9S12GC-Family
0
0
5
5
DDRAD4
RDRAD4
Rev 01.24
0
0
4
4
Description
Description
DDRAD3
RDRAD3
0
0
3
3
DDRAD2
RDRAD2
0
0
2
2
DDRAD1
RDRAD1
Freescale Semiconductor
0
0
1
1
DDRAD0
RDRAD0
0
0
0
0
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