MC9S12C128MFAE Freescale Semiconductor, MC9S12C128MFAE Datasheet - Page 312
![IC MCU 128K FLASH 25MHZ 48-LQFP](/photos/12/20/122066/mc9s12c128mfae_sml.jpg)
MC9S12C128MFAE
Manufacturer Part Number
MC9S12C128MFAE
Description
IC MCU 128K FLASH 25MHZ 48-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Specifications of MC9S12C128MFAE
Core Processor
HCS12
Core Size
16-Bit
Speed
25MHz
Connectivity
CAN, EBI/EMI, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
31
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.35 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
48-LQFP
Processor Series
S12C
Core
HCS12
Data Bus Width
16 bit
Data Ram Size
4 KB
Interface Type
CAN/SCI/SPI
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
31
Number Of Timers
8
Operating Supply Voltage
3.3 V to 5.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
M68EVB912C32EE
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Package
48LQFP
Family Name
HCS12
Maximum Speed
25 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC9S12C128MFAE
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Module Base + 0x0014 (CANIDMR0)
Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV2)
10.3.2.17 MSCAN Identifier Mask Registers (CANIDMR0–CANIDMR7)
The identifier mask register specifies which of the corresponding bits in the identifier acceptance register
are relevant for acceptance filtering. To receive standard identifiers in 32 bit filter mode, it is required to
program the last three bits (AM[2:0]) in the mask registers CANIDMR1 and CANIDMR5 to “don’t care.”
To receive standard identifiers in 16 bit filter mode, it is required to program the last three bits (AM[2:0])
in the mask registers CANIDMR1, CANIDMR3, CANIDMR5, and CANIDMR7 to “don’t care.”
Read: Anytime
Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1)
312
AM[7:0]
Field
7:0
Reset
Reset
Reset
Reset
Figure 10-21. MSCAN Identifier Mask Registers (First Bank) — CANIDMR0–CANIDMR3
W
W
W
W
R
R
R
R
0x0015 (CANIDMR1)
0x0016 (CANIDMR2)
0x0017 (CANIDMR3)
Acceptance Mask Bits — If a particular bit in this register is cleared, this indicates that the corresponding bit in
the identifier acceptance register must be the same as its identifier bit before a match is detected. The message
is accepted if all such bits match. If a bit is set, it indicates that the state of the corresponding bit in the identifier
acceptance register does not affect whether or not the message is accepted.
0 Match corresponding acceptance code register and identifier bits
1 Ignore corresponding acceptance code register bit
AM7
AM7
AM7
AM7
0
0
0
0
7
7
7
7
Table 10-21. CANIDMR0–CANIDMR3 Register Field Descriptions
AM6
AM6
AM6
AM6
6
0
6
0
6
0
6
0
MC9S12C-Family / MC9S12GC-Family
AM5
AM5
AM5
AM5
0
0
0
0
5
5
5
5
Rev 01.24
AM4
AM4
AM4
AM4
4
0
4
0
4
0
4
0
Description
AM3
AM3
AM3
AM3
0
0
0
0
3
3
3
3
AM2
AM2
AM2
AM2
2
0
2
0
2
0
2
0
Freescale Semiconductor
AM1
AM1
AM1
AM1
0
0
0
0
1
1
1
1
AM0
AM0
AM0
AM0
0
0
0
0
0
0
0
0
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