MC9S12C128MFAE Freescale Semiconductor, MC9S12C128MFAE Datasheet - Page 96
![IC MCU 128K FLASH 25MHZ 48-LQFP](/photos/12/20/122066/mc9s12c128mfae_sml.jpg)
MC9S12C128MFAE
Manufacturer Part Number
MC9S12C128MFAE
Description
IC MCU 128K FLASH 25MHZ 48-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Specifications of MC9S12C128MFAE
Core Processor
HCS12
Core Size
16-Bit
Speed
25MHz
Connectivity
CAN, EBI/EMI, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
31
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.35 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
48-LQFP
Processor Series
S12C
Core
HCS12
Data Bus Width
16 bit
Data Ram Size
4 KB
Interface Type
CAN/SCI/SPI
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
31
Number Of Timers
8
Operating Supply Voltage
3.3 V to 5.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
M68EVB912C32EE
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Package
48LQFP
Family Name
HCS12
Maximum Speed
25 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC9S12C128MFAE
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Chapter 2 Port Integration Module (PIM9C32) Block Description
2.3.2.4.7
Read: Anytime.
Write: Anytime.
2.3.2.4.8
Read: Anytime.
Write: Anytime.
96
Module Base + 0x001E
Module Base + 0x001F
PIEP[7:0]
PIFP[7:0]
Reset
Reset
Field
Field
7–0
7–0
W
W
R
R
PIEP7
PIFP7
Pull Select Port P — This register disables or enables on a per pin basis the edge sensitive external interrupt
associated with port P.
0 Interrupt is disabled (interrupt flag masked).
1 Interrupt is enabled.
Interrupt Flags Port P — Each flag is set by an active edge on the associated input pin. This could be a rising
or a falling edge based on the state of the PPSP register. To clear this flag, write a “1” to the corresponding bit
in the PIFP register. Writing a “0” has no effect.
0 No active edge pending.
1 Active edge on the associated bit has occurred (an interrupt will occur if the associated enable bit is set).
0
0
7
7
Writing a “0” has no effect.
Writing a “1” clears the associated flag.
Port P Interrupt Enable Register (PIEP)
Port P Interrupt Flag Register (PIFP)
PIEP6
PIFP6
0
0
6
6
Figure 2-30. Port P Interrupt Enable Register (PIEP)
Figure 2-31. Port P Interrupt Flag Register (PIFP)
Table 2-26. PIEP Field Descriptions
Table 2-27. PIFP Field Descriptions
PIEP5
PIFP5
MC9S12C-Family / MC9S12GC-Family
0
0
5
5
PIEP4
PIFP4
Rev 01.24
0
0
4
4
Description
Description
PIEP3
PIFP3
0
0
3
3
PIEP2
PIFP2
0
0
2
2
Freescale Semiconductor
PIEP1
PIFP1
0
0
1
1
PIEP0
PIFP0
0
0
0
0
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