MC9S12C128MFAE Freescale Semiconductor, MC9S12C128MFAE Datasheet - Page 557
![IC MCU 128K FLASH 25MHZ 48-LQFP](/photos/12/20/122066/mc9s12c128mfae_sml.jpg)
MC9S12C128MFAE
Manufacturer Part Number
MC9S12C128MFAE
Description
IC MCU 128K FLASH 25MHZ 48-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Specifications of MC9S12C128MFAE
Core Processor
HCS12
Core Size
16-Bit
Speed
25MHz
Connectivity
CAN, EBI/EMI, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
31
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.35 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
48-LQFP
Processor Series
S12C
Core
HCS12
Data Bus Width
16 bit
Data Ram Size
4 KB
Interface Type
CAN/SCI/SPI
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
31
Number Of Timers
8
Operating Supply Voltage
3.3 V to 5.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
M68EVB912C32EE
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Package
48LQFP
Family Name
HCS12
Maximum Speed
25 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC9S12C128MFAE
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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19.3.2.14 RESERVED6
This register is reserved for factory testing and is not accessible to the user.
All bits read 0 and are not writable.
19.4
19.4.1
Write operations are used for the program, erase, and erase verify algorithms described in this section. The
program and erase algorithms are controlled by a state machine whose timebase FCLK is derived from the
oscillator clock via a programmable divider. The FCMD register as well as the associated FADDR and
FDATA registers operate as a buffer and a register (2-stage FIFO) so that a new command along with the
necessary data and address can be stored to the buffer while the previous command is still in progress. This
pipelined operation allows a time optimization when programming more than one word on a specific row,
as the high voltage generation can be kept active in between two programming commands. The pipelined
operation also allows a simplification of command launching. Buffer empty as well as command
completion are signalled by flags in the FSTAT register with corresponding interrupts generated, if
enabled.
The next sections describe:
19.4.1.1
Prior to issuing any Flash command after a reset, it is first necessary to write the FCLKDIV register to
divide the oscillator clock down to within the 150-kHz to 200-kHz range. Since the program and erase
timings are also a function of the bus clock, the FCLKDIV determination must take this information into
account.
If we define:
Freescale Semiconductor
Module Base + 0x000F
Reset
•
•
•
•
•
W
R
How to write the FCLKDIV register
Command write sequence used to program, erase or erase verify the Flash array
Valid Flash commands
Errors resulting from illegal Flash operations
FCLK as the clock of the Flash timing control block
Functional Description
Flash Command Operations
Writing the FCLKDIV Register
0
0
7
= Unimplemented or Reserved
0
0
6
MC9S12C-Family / MC9S12GC-Family
0
0
5
Figure 19-23. RESERVED6
Rev 01.24
0
0
4
0
0
3
Chapter 19 64 Kbyte Flash Module (S12FTS64KV4)
0
0
2
0
0
1
0
0
0
557
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