MC9S12C128MFAE Freescale Semiconductor, MC9S12C128MFAE Datasheet - Page 239
![IC MCU 128K FLASH 25MHZ 48-LQFP](/photos/12/20/122066/mc9s12c128mfae_sml.jpg)
MC9S12C128MFAE
Manufacturer Part Number
MC9S12C128MFAE
Description
IC MCU 128K FLASH 25MHZ 48-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Specifications of MC9S12C128MFAE
Core Processor
HCS12
Core Size
16-Bit
Speed
25MHz
Connectivity
CAN, EBI/EMI, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
31
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.35 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
48-LQFP
Processor Series
S12C
Core
HCS12
Data Bus Width
16 bit
Data Ram Size
4 KB
Interface Type
CAN/SCI/SPI
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
31
Number Of Timers
8
Operating Supply Voltage
3.3 V to 5.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
M68EVB912C32EE
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Package
48LQFP
Family Name
HCS12
Maximum Speed
25 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC9S12C128MFAE
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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8.3.2.8
Read: Anytime, returns unpredictable values
Write: Anytime in special modes, unimplemented in normal modes
Freescale Semiconductor
Module Base + 0x0008
CC[2:0]
FIFOR
Reset
Field
2–0
4
W
R
FIFO Over Run Flag — This bit indicates that a result register has been written to before its associated
conversion complete flag (CCF) has been cleared. This flag is most useful when using the FIFO mode because
the flag potentially indicates that result registers are out of sync with the input channels. However, it is also
practical for non-FIFO modes, and indicates that a result register has been over written before it has been read
(i.e. the old data has been lost). This flag is cleared when one of the following occurs:
0 No over run has occurred
1 An over run condition exists
Conversion Counter — These 3 read-only bits are the binary value of the conversion counter. The conversion
counter points to the result register that will receive the result of the current conversion. For example, CC2 = 1,
CC1 = 1, CC0 = 0 indicates that the result of the current conversion will be in ATD Result Register 6. If in non-
FIFO mode (FIFO = 0) the conversion counter is initialized to zero at the begin and end of the conversion
sequence. If in FIFO mode (FIFO = 1) the register counter is not initialized. The conversion counters wraps
around when its maximum value is reached.
Aborting a conversion or starting a new conversion by write to an ATDCTL register (ATDCTL5-2) clears the
conversion counter even if FIFO=1.
Reserved Register (ATDTEST0)
U
1
7
Writing to this registers when in special modes can alter functionality.
A) Write “1” to FIFOR
B) Start a new conversion sequence (write to ATDCTL5 or external trigger)
= Unimplemented or Reserved
U
0
6
Table 8-13. ATDSTAT0 Field Descriptions (continued)
Figure 8-10. Reserved Register (ATDTEST0)
MC9S12C-Family / MC9S12GC-Family
U
0
5
Rev 01.24
NOTE
U
0
4
Chapter 8 Analog-to-Digital Converter (ATD10B8C) Block Description
Description
U
0
3
U
0
2
U
0
1
U
0
0
239
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