MC9S12C128MFAE Freescale Semiconductor, MC9S12C128MFAE Datasheet - Page 261
![IC MCU 128K FLASH 25MHZ 48-LQFP](/photos/12/20/122066/mc9s12c128mfae_sml.jpg)
MC9S12C128MFAE
Manufacturer Part Number
MC9S12C128MFAE
Description
IC MCU 128K FLASH 25MHZ 48-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Specifications of MC9S12C128MFAE
Core Processor
HCS12
Core Size
16-Bit
Speed
25MHz
Connectivity
CAN, EBI/EMI, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
31
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.35 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
48-LQFP
Processor Series
S12C
Core
HCS12
Data Bus Width
16 bit
Data Ram Size
4 KB
Interface Type
CAN/SCI/SPI
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
31
Number Of Timers
8
Operating Supply Voltage
3.3 V to 5.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
M68EVB912C32EE
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Package
48LQFP
Family Name
HCS12
Maximum Speed
25 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC9S12C128MFAE
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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9.3.2.7
This register controls the PLL functionality.
Read: anytime
Write: refer to each bit for individual write conditions
Freescale Semiconductor
Module Base + 0x0006
COPWAI
RTIWAI
PLLON
Reset
CWAI
Field
Field
CME
2
1
0
7
6
W
R
CME
Core Stops in Wait Mode Bit — Write: anytime
0 Core clock keeps running in wait mode.
1 Core clock stops in wait mode.
RTI Stops in Wait Mode Bit — Write: anytime
0 RTI keeps running in wait mode.
1 RTI stops and initializes the RTI dividers whenever the part goes into wait mode.
COP Stops in Wait Mode Bit — Normal modes: Write once —Special modes: Write anytime
0 COP keeps running in wait mode.
1 COP stops and initializes the COP dividers whenever the part goes into wait mode.
Clock Monitor Enable Bit — CME enables the clock monitor. Write anytime except when SCM = 1.
0 Clock monitor is disabled.
1 Clock monitor is enabled. Slow or stopped clocks will cause a clock monitor reset sequence or self-clock
Note: Operating with CME = 0 will not detect any loss of clock. In case of poor clock quality this could cause
Note: In Stop Mode (PSTP = 0) the clock monitor is disabled independently of the CME bit setting and any loss
Phase Lock Loop On Bit — PLLON turns on the PLL circuitry. In self-clock mode, the PLL is turned on, but the
PLLON bit reads the last latched value. Write anytime except when PLLSEL = 1.
0 PLL is turned off.
1 PLL is turned on. If AUTO bit is set, the PLL will lock automatically.
CRG PLL Control Register (PLLCTL)
1
7
mode.
unpredictable operation of the MCU.
of clock will not be detected.
= Unimplemented or Reserved
PLLON
1
6
Table 9-4. CLKSEL Field Descriptions (continued)
Figure 9-10. CRG PLL Control Register (PLLCTL)
Table 9-5. PLLCTL Field Descriptions
AUTO
MC9S12C-Family / MC9S12GC-Family
1
5
Rev 01.24
ACQ
1
4
Chapter 9 Clocks and Reset Generator (CRGV4) Block Description
Description
Description
0
0
3
PRE
0
2
PCE
0
1
SCME
1
0
261
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