MC9S12C128MFAE Freescale Semiconductor, MC9S12C128MFAE Datasheet - Page 150
![IC MCU 128K FLASH 25MHZ 48-LQFP](/photos/12/20/122066/mc9s12c128mfae_sml.jpg)
MC9S12C128MFAE
Manufacturer Part Number
MC9S12C128MFAE
Description
IC MCU 128K FLASH 25MHZ 48-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Specifications of MC9S12C128MFAE
Core Processor
HCS12
Core Size
16-Bit
Speed
25MHz
Connectivity
CAN, EBI/EMI, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
31
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.35 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
48-LQFP
Processor Series
S12C
Core
HCS12
Data Bus Width
16 bit
Data Ram Size
4 KB
Interface Type
CAN/SCI/SPI
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
31
Number Of Timers
8
Operating Supply Voltage
3.3 V to 5.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
M68EVB912C32EE
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Package
48LQFP
Family Name
HCS12
Maximum Speed
25 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC9S12C128MFAE
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Chapter 4 Multiplexed External Bus Interface (MEBIV3)
4.3.2.16
Read: Anytime
Write: Anytime
This register determines the primary direction for each port K pin configured as general-purpose I/O. This
register is not in the map in peripheral or expanded modes while the EMK control bit in MODE register is
set. Therefore, these accesses will be echoed externally.
4.4
4.4.1
The external signals LSTRB, R/W, and AB0 indicate the type of bus access that is taking place. Accesses
to the internal RAM module are the only type of access that would produce LSTRB = AB0 = 1, because
the internal RAM is specifically designed to allow misaligned 16-bit accesses in a single cycle. In these
cases the data for the address that was accessed is on the low half of the data bus and the data for
address + 1 is on the high half of the data bus. This is summarized in
150
Module Base + 0x0033
Starting address location affected by INITRG register setting.
DDRK
Field
7:0
Reset
W
R
Functional Description
Detecting Access Type from External Signals
Data Direction Port K Bits
0 Associated pin is a high-impedance input
1 Associated pin is an output
Note: It is unwise to write PORTK and DDRK as a word access. If you are changing port K pins from inputs to
Note: To ensure that you read the correct value from the PORTK pins, always wait at least one cycle after writing
Port K Data Direction Register (DDRK)
Bit 7
0
7
outputs, the data may have extra transitions during the write. It is best to initialize PORTK before enabling
as outputs.
to the DDRK register before reading from the PORTK register.
LSTRB
1
0
1
0
Figure 4-20. Port K Data Direction Register (DDRK)
6
0
6
Table 4-15. Access Type vs. Bus Control Pins
AB0
Table 4-14. EBICTL Field Descriptions
0
1
0
1
MC9S12C-Family / MC9S12GC-Family
5
0
5
R/W
1
1
0
0
Rev 01.24
4
0
4
Description
8-bit read of an even address
8-bit read of an odd address
8-bit write of an even address
8-bit write of an odd address
3
3
0
Type of Access
Table
2
2
0
4-15.
Freescale Semiconductor
1
0
1
Bit 0
0
0
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