MC9S12C128MFAE Freescale Semiconductor, MC9S12C128MFAE Datasheet - Page 549
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MC9S12C128MFAE
Manufacturer Part Number
MC9S12C128MFAE
Description
IC MCU 128K FLASH 25MHZ 48-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Specifications of MC9S12C128MFAE
Core Processor
HCS12
Core Size
16-Bit
Speed
25MHz
Connectivity
CAN, EBI/EMI, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
31
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.35 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
48-LQFP
Processor Series
S12C
Core
HCS12
Data Bus Width
16 bit
Data Ram Size
4 KB
Interface Type
CAN/SCI/SPI
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
31
Number Of Timers
8
Operating Supply Voltage
3.3 V to 5.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
M68EVB912C32EE
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Package
48LQFP
Family Name
HCS12
Maximum Speed
25 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC9S12C128MFAE
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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FPHDIS is cleared. The FPROT register is loaded from Flash address 0xFF0D during the reset sequence,
indicated by F in
To change the Flash protection that will be loaded on reset, the upper sector of the Flash array must be
unprotected, then the Flash protection byte located at Flash address 0xFF0D must be written to.
A protected Flash sector is disabled by FPHDIS
defined by FPHS[1:0]
Trying to alter any of the protected areas will result in a protect violation error and the PVIOL flag will be
set in the FSTAT register (see
when protection is fully disabled by setting the
erase a Flash array while protection is enabled will set the PVIOL flag in the FSTAT register.
Freescale Semiconductor
FPHS[1:0]
FPLS[1:0]
FPOPEN
FPHDIS
FPLDIS
Field
NV6
4–3
1–0
7
6
5
2
Protection Function for Program or Erase — It is possible using the FPOPEN bit to either select address
ranges to be protected using FPHDIS, FPLDIS, FPHS[1:0] and FPLS[1:0] or to select the same ranges to be
unprotected. When FPOPEN is set, FPxDIS enables the ranges to be protected, whereby clearing FPxDIS
enables protection for the range specified by the corresponding FPxS[1:0] bits. When FPOPEN is cleared,
FPxDIS defines unprotected ranges as specified by the corresponding FPxS[1:0] bits. In this case, setting
FPxDIS enables protection. Thus the effective polarity of the FPxDIS bits is swapped by the FPOPEN bit as
shown in
can remain unprotected for EEPROM emulation.
0 The FPHDIS and FPLDIS bits define Flash address ranges to be unprotected
1 The FPHDIS and FPLDIS bits define Flash address ranges to be protected
Nonvolatile Flag Bit — The NV6 bit should remain in the erased state for future enhancements.
Flash Protection Higher Address Range Disable — The FPHDIS bit determines whether there is a
protected/unprotected area in the higher space of the Flash address map.
0 Protection/unprotection enabled
1 Protection/unprotection disabled
Flash Protection Higher Address Size — The FPHS[1:0] bits determine the size of the protected/unprotected
sector as shown in
Flash Protection Lower Address Range Disable — The FPLDIS bit determines whether there is a
protected/unprotected sector in the lower space of the Flash address map.
0 Protection/unprotection enabled
1 Protection/unprotection disabled
Flash Protection Lower Address Size — The FPLS[1:0] bits determine the size of the protected/unprotected
sector as shown in
Figure
Table
and FPLS[1:0]
19-10.
19-10. This function allows the main part of the Flash array to be protected while a small range
Table
Table
Section
19-11. The FPHS[1:0] bits can only be written to while the FPHDIS bit is set.
19-12. The FPLS[1:0] bits can only be written to while the FPLDIS bit is set.
Table 19-9. FPROT Field Descriptions
MC9S12C-Family / MC9S12GC-Family
in the FPROT register.
19.3.2.6). A mass erase of the whole Flash array is only possible
FPOPEN, FPLDIS,
and FPLDIS
Rev 01.24
Description
while the size of the protected sector is
Chapter 19 64 Kbyte Flash Module (S12FTS64KV4)
and FPHDIS bits. An attempt to mass
549
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