MC9S12C128MFAE Freescale Semiconductor, MC9S12C128MFAE Datasheet - Page 297
![IC MCU 128K FLASH 25MHZ 48-LQFP](/photos/12/20/122066/mc9s12c128mfae_sml.jpg)
MC9S12C128MFAE
Manufacturer Part Number
MC9S12C128MFAE
Description
IC MCU 128K FLASH 25MHZ 48-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Specifications of MC9S12C128MFAE
Core Processor
HCS12
Core Size
16-Bit
Speed
25MHz
Connectivity
CAN, EBI/EMI, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
31
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.35 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
48-LQFP
Processor Series
S12C
Core
HCS12
Data Bus Width
16 bit
Data Ram Size
4 KB
Interface Type
CAN/SCI/SPI
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
31
Number Of Timers
8
Operating Supply Voltage
3.3 V to 5.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
M68EVB912C32EE
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Package
48LQFP
Family Name
HCS12
Maximum Speed
25 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC9S12C128MFAE
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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10.3.2.3
The CANBTR0 register configures various CAN bus timing parameters of the MSCAN module.
Read: Anytime
Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1)
Freescale Semiconductor
Module Base + 0x0002
SJW[1:0]
BRP[5:0]
Field
7:6
5:0
Reset:
W
R
BRP5
Synchronization Jump Width — The synchronization jump width defines the maximum number of time quanta
(Tq) clock cycles a bit can be shortened or lengthened to achieve resynchronization to data transitions on the
CAN bus (see
Baud Rate Prescaler — These bits determine the time quanta (Tq) clock which is used to build up the bit timing
(see
MSCAN Bus Timing Register 0 (CANBTR0)
0
0
0
0
1
:
SJW1
Table
0
7
SJW1
BRP4
10-5).
0
0
1
1
0
0
0
0
1
:
Table
Figure 10-6. MSCAN Bus Timing Register 0 (CANBTR0)
Table 10-4. Synchronization Jump Width
SJW0
Table 10-3. CANBTR0 Register Field Descriptions
BRP3
6
0
10-4).
0
0
0
0
1
:
Table 10-5. Baud Rate Prescaler
MC9S12C-Family / MC9S12GC-Family
BRP2
BRP5
0
0
0
0
1
:
0
5
SJW0
BRP1
0
1
0
1
0
0
1
1
1
:
Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV2)
Rev 01.24
BRP4
4
0
BRP0
Description
0
1
0
1
1
:
BRP3
Synchronization Jump Width
0
3
Prescaler value (P)
2 Tq clock cycles
3 Tq clock cycles
4 Tq clock cycles
1 Tq clock cycle
BRP2
64
2
0
1
2
3
4
:
BRP1
0
1
BRP0
0
0
297
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